As digital transformation accelerates, the demand for high-performance, energy-efficient, and highly integrated semiconductor devices is pushing conventional silicon technology toward its fundamental scaling limits [1]. Three-dimensional stacked field-effect transistors based on two-dimensional materials have emerged as a promising pathway for next-generation logic technologies, owing to their atomically thin bodies, superior electrostatic control, and compatibility with vertical integration. While silicon technology is evolving toward gate-all-around architectures with four-sided gate control, directly translating this concept to 2D material channels remains challenging because of their atomic-scale thickness, interface sensitivity, and process limitations [2]. Therefore, rather than simply replicating silicon-based device paradigms, it is essential to determine the gate architecture and channel thickness that are intrinsically optimized for 2D materials. In addition, reliable and low-resistance interconnection is a key enabler for three-dimensional stacked systems, where signal delay, power consumption, and thermal stability are strongly influenced by the interconnect material system [3].

In this talk, I will present our experimental investigations into how gate configuration and channel layer number affect the electrical performance of 2D-material-based transistors, with the goal of identifying device architectures that fully leverage the unique advantages of 2D channels. I will also introduce our recent work on novel interconnect materials, including their thin-film growth, structural and electrical characterization, and potential relevance to future 3D-integrated logic technologies. 

References

[1] S. H. Shin. et al., Nano. Lett. 25 (18), 7224–7233, 2025

[2] H. H. Yoon et. al., npj 2D Materials and Applications, 9 (1) 68, 2025

[3] H. Kim et. al.,  Nat. Rev. Elect. Eng. 2, 835-845, 2025

With the rapid acceleration of the digital transformation era, the continued miniaturization of electronic devices has led to an unprecedented increase in device density and interconnect complexity, thereby driving the demand for high-speed data storage, processing, and communication within increasingly compact form factors [1,2]. At the same time, the rapid expansion of artificial intelligence (AI)-enabled space technologies is accelerating the adoption of cost-effective commercial off-the-shelf (COTS) electronic devices in radiation-rich environments [3]. In particular, neuromorphic computing, which integrates data storage and processing within a single device, has emerged as a promising solution for efficient AI computation in space systems [4]. However, in such applications, radiation-induced degradation or device failure can lead to critical system-level malfunctions, making device reliability under extreme environments a key requirement.

In this study, we systematically investigate the reliability of two-dimensional (2D) material-based resistive random-access memory (RRAM) devices for next-generation neuromorphic computing in extreme radiation environments. Owing to their atomically thin structures, 2D materials are expected to exhibit enhanced tolerance to radiation-induced defect formation and charge trapping, making them a promising platform for highly durable neuromorphic devices capable of operating in harsh environments. We select Te, MoS2, and h-BN as representative active-layer materials and comparatively examine the stability, degradation behavior, and key reliability issues of each material system under radiation exposure. In addition, we discuss possible material- and device- engineering strategies to mitigate radiation-induced degradation and improve operational stability.

References

[1]   S. H. Shin. et al., Nano Letters, Mini Review, 25 (18), 7224–7233 (2025)

[2]   H. H. Yoon. et al., npj 2d materials and applications, 9 (68), 1-11 (2025)

[3]   Budroweit, J. et al., Electronics, 10(9), 1008 (2021)

[4]   F. Ortiz et al., IEEE Transactions on Machine Learning in Communications and Networking, 2, 169-189 (2024)

As silicon scaling approaches its fundamental limits, new materials are needed for next-generation logic and interconnect technologies. This talk presents a Te-based p-type 2D semiconductor for MoS₂-compatible CMOS integration and low-resistivity MoP topological semimetal thin films as promising candidates for future interconnects.

References

[1] S. H. Shin. et al., Nano. Lett. 25 (18), 7224–7233, 2025

[2] H. H. Yoon et. al., npj 2D Materials and Applications, 9 (1) 68, 2025

[3] H. Kim et. al.,  Nat. Rev. Elect. Eng. 2, 835-845, 2025

With the rapid advancement of digital transformation, continued device miniaturization has dramatically increased device density and interconnect complexity, creating strong demand for high-speed data storage, processing, and communication within increasingly compact form factors [1,2]. However, as interconnect dimensions continue to shrink, electrical performance degradation has emerged as a key bottleneck to further system-level scaling. Topological semimetals have attracted attention as promising next-generation interconnect materials because their unusual electronic structures may support efficient charge transport at reduced dimensions [3]. In particular, molybdenum phosphide (MoP) and niobium phosphide (NbP) have been reported to exhibit resistivities comparable to or lower than that of Cu in the sub-10 nm regime, although their performance still falls short of theoretical predictions [4,5]. Despite this promise, a systematic understanding of the effects of crystal orientation, grain size, and grain boundary structure on electron transport remains limited. In this study, we investigate the electron transport behavior of MoP as a function of crystal orientation, grain size, and grain boundary structure. MoP films are synthesized by phosphorization, with their nanostructure controlled through precursor and substrate selection. Macroscopic transport properties are evaluated using Hall-bar measurements, while local electronic states are probed by STM/STS to identify the microstructural origin of transport variation. Our results provide insight into the transport mechanisms of MoP and suggest material design strategies for reducing microstructure-induced transport degradation in topological semimetal interconnects.

References

[1] S. H. Shin, D.-H. Kang, H. H. Yoon, J. Y. Park, M. Song, H. Son, D. Ha, H.-J. Shin, Nano Letters 2025, 25, 7224.

[2] H. H. Yoon, J. Y. Park, Y. T. Megra, J. H. Baek, M. Song, D. Akinwande, D. Ha, D.-H. Kang, H.-J. Shin, npj 2D Materials and Applications 2025, 9, 68.

[3] H. Kim, S. Oh, S. An, J. Kim, T. Kim, S. Jeong, O. Kaya, T. Galvani, S. Roche, J. J. Cha, M. Chhowalla, H. S. Shin, H.-J. Shin, Nature Reviews Electrical Engineering 2025, 2, 835.

[4] H. J.Han, S.Kumar, G.Jin, X.Ji, J. L.Hart, D. J.Hynek, Q. P.Sam, V.Hasse, C.Felser, D. G.Cahill, R.Sundararaman, J. J.Cha, Adv. Mater.2023, 35, 2208965.

[5] A. I. Khan, A. Ramdas, E. Lindgren, H.-M. Kim, B. Won, X. Wu, K. Saraswat, C.-T. Chen, Y. Suzuki, F. H. da Jornada, I.-K. Oh, E. Pop, Science 2025, 387, 62.

As digital transformation accelerates, the exponential increase in data generation places unprecedented demands on semiconductor devices for higher performance, energy efficiency, and integration density. However, conventional silicon-based transistors are approaching their fundamental scaling limits. [1,2] Two-dimensional (2D) materials have emerged as promising candidates for next-generation semiconductor channel materials in place of silicon. Among them, tellurium has attracted considerable attention as a potential p-type channel material because of its intrinsic p-type characteristics, excellent electrical properties, and surface stability. However, several critical challenges remain for practical device applications, including its thickness-dependent bandgap variation (from ~0.35 eV to over 1 eV) [3], the difficulty of precise thickness control, limitations in large-area synthesis, and the relatively low on/off ratio, which is typically limited to the 103–104 range in transfer characteristics.

In this study, large-area tellurium thin films were deposited by a sputtering process, and their thickness was systematically controlled by adjusting the sputtering power. To overcome the limitations of pristine tellurium channels, oxidation and subsequent chalcogen doping were employed to modify the film properties and improve device switching behavior. Through this approach, we demonstrate enhanced on/off ratio and improved electrical characteristics, highlighting the potential of engineered tellurium–based channels as promising high-performance p-type materials for next-generation electronic devices. 

References

[1] S. H. Shin. et al., Nano. Lett. 25 (18), 7224–7233, 2025

[2] H. H. Yoon. et al., npj 2d materials and applications, 9 (68), 1-11 (2025)

[3] Qiu, Gang, et al., npj 2D Materials and Applications, 6.1 (2022): 17.

As silicon scaling approaches its fundamental limits, new materials are needed for next-generation logic and interconnect technologies. This talk presents a Te-based p-type 2D semiconductor for MoS₂-compatible CMOS integration and low-resistivity MoP topological semimetal thin films as promising candidates for future interconnects.

References

[1] S. H. Shin. et al., Nano. Lett. 25 (18), 7224–7233, 2025

[2] H. H. Yoon et. al., npj 2D Materials and Applications, 9 (1) 68, 2025

[3] H. Kim et. al.,  Nat. Rev. Elect. Eng. 2, 835-845, 2025

Two-dimensional (2D) materials have emerged as promising candidates for next-generation semiconductor channel materials. While n-type materials have seen long-standing advancements in research, p-type materials have lagged behind due to their scarcity[1]. Tellurium, which exhibits intrinsic p-type characteristics along with excellent electrical performance and surface stability, has attracted attention as a next-generation p-type semiconductor channel material. However, its thickness-dependent bandgap variation (0.35 eV to over 1 eV) [2] and the challenges associated with precise thickness control and large-area synthesis remain major obstacles.

In this study, tellurium films deposited via sputtering were oxidized to form tellurium oxide structures, which were then systematically characterized. The oxidized tellurium films were fabricated into thin-film transistors (TFTs), and their electrical performance and device characteristics were evaluated. Furthermore, chemical doping with AuCl₃ significantly improves the on/off current ratio and carrier concentration of Te oxide films. This method provides a simple and effective approach to improving device performance and enables the tellurium oxide as a high-performance p-type channel material.

References

[1] Xiong, Yunhai, et al. Advanced Materials 35.50 (2023)

[2] Qiu, Gang, et al. "The resurrection of tellurium as an elemental two-dimensional semiconductor." npj 2D Materials and Applications 6.1 (2022): 17.

Topological semimetals (TSMs) have recently attracted significant attention as promising candidates for next-generation interconnect materials, owing to their unique spin-polarized and backscattering-protected charge transport -originating from topologically protected nodes in their band structures [1]. In particular, Weyl semimetals such as MoP₂, WP₂, NbP, and TaP exhibit three-dimensional gapless states, along with advantageous properties for interconnect applications, including high carrier density, low residual resistivity, and long electron mean free paths [2–3].

To date, research has been heavily concentrated on materials like MoP and NbP. However, recent theoretical and experimental reports suggest that TaP may exhibit even better resistivity performance, attributed to its closely aligned Weyl nodes near the Fermi level, strong spin–orbit coupling, and higher Fermi velocity compared to NbP [4-6].

To explore the full potential of these materials for nano electronic integration, both electrical property analysis and large-area thin film synthesis are essential. In this study, we demonstrate the successful chemical vapor deposition (CVD) growth of TaP thin films, and perform a comparative analysis of their structural and electrical properties with NbP and MoP.

These findings aim to provide a foundation for integrating Weyl TSMs in advanced interconnect technologies and highlight the potential of underexplored topological materials for future device applications

References

[1] E. Zhai, T. Liang, R. Liu, M. Cai, R. Li, Q. Shao, C. Su, Y. Cosmi “The rise of semi-metal electronics. Nature Reviews Electrical Engineering”, 1-19 (2024)

[2] G. Resta, S.-T. Pi, X. Wan, and S. Y. Savrasov. "High surface conductivity of Fermi-arc electrons in Weyl semimetals." Physical Review B 97, 085142 (2018)

[3] H. J. Han, S. Kumar, G. Jin, X. Ji, J. L. Hart, D. J. Hynek, Q. P. Sam, V. Hasse, C. Felser, D. G. Cahill, R. Sundararaman, and J. J. Cha. “Topological metal MoP nanowire for interconnect”, Advanced Materials 35, 2208965 (2023)

[4] C.-C. Lee, S.-Y. Xu, S.-M. Huang, D. S. Sanchez, I. Belopolski, G. Chang, G. Bian, N. Alidoust, and H. Zheng. “Fermi surface interconnectivity and topology in Weyl fermion semimetals TaAs, TaP, NbAs, and NbP”, Phys. Rev. B 92, 235104 (2015)

[5] D. Sapkota, R. Mukherjee, and D. Mandrus. “Single Crystal Growth, Resistivity, and Electronic Structure of the Weyl Semimetals NbP and TaP. Crystals”, 6, 10 (2016)

[6] F. Arnold, C. Shekhar, S.-C. Wu, Y. Sun, R. D. dos Reis, N. Kumar, M. Naumann, M. O. Ajeesh, M. Schmidt, A. G. Grushin, J. H. Bardarson, M. Baenitz, D. Sokolov, H. Borrmann, M. Nicklas, C. Felser, E. Hassinger, and B. Yan. “Negative magnetoresistance without well-defined chirality in the Weyl semimetal TaP”, Nat Commun 7, 11615 (2016)

Two-dimensional (2D) materials have emerged as promising candidates for next-generation semiconductor channel materials. While n-type materials have seen long-standing advancements in research, p-type materials have lagged behind due to their scarcity[1]. Tellurium, which exhibits intrinsic p-type characteristics along with excellent electrical performance and surface stability, has attracted attention as a next-generation p-type semiconductor channel material. However, its thickness-dependent bandgap variation (0.35 eV to over 1 eV) [2] and the challenges associated with precise thickness control and large-area synthesis remain major obstacles.

In this study, tellurium films deposited via sputtering were oxidized to form tellurium oxide structures, which were then systematically characterized. The oxidized tellurium films were transferred to fabricate thin-film transistors (TFTs), and their electrical performance and device characteristics were evaluated. Furthermore, selenium doping was introduced into the tellurium oxide films, resulting in enhanced carrier mobility and improved device stability, which is expected to demonstrate the potential of selenium-doped tellurium oxide as a high-performance p-type channel material.

References

[1] Xiong, Yunhai, et al. Advanced Materials 35.50 (2023)

[2] Qiu, Gang, et al. "The resurrection of tellurium as an elemental two-dimensional semiconductor." npj 2D Materials and Applications 6.1 (2022): 17.