As digital transformation accelerates, the demand for high-performance, energy-efficient, and highly integrated semiconductor devices is pushing conventional silicon technology toward its fundamental scaling limits [1]. Three-dimensional stacked field-effect transistors based on two-dimensional materials have emerged as a promising pathway for next-generation logic technologies, owing to their atomically thin bodies, superior electrostatic control, and compatibility with vertical integration. While silicon technology is evolving toward gate-all-around architectures with four-sided gate control, directly translating this concept to 2D material channels remains challenging because of their atomic-scale thickness, interface sensitivity, and process limitations [2]. Therefore, rather than simply replicating silicon-based device paradigms, it is essential to determine the gate architecture and channel thickness that are intrinsically optimized for 2D materials. In addition, reliable and low-resistance interconnection is a key enabler for three-dimensional stacked systems, where signal delay, power consumption, and thermal stability are strongly influenced by the interconnect material system [3].

In this talk, I will present our experimental investigations into how gate configuration and channel layer number affect the electrical performance of 2D-material-based transistors, with the goal of identifying device architectures that fully leverage the unique advantages of 2D channels. I will also introduce our recent work on novel interconnect materials, including their thin-film growth, structural and electrical characterization, and potential relevance to future 3D-integrated logic technologies. 

References

[1] S. H. Shin. et al., Nano. Lett. 25 (18), 7224–7233, 2025

[2] H. H. Yoon et. al., npj 2D Materials and Applications, 9 (1) 68, 2025

[3] H. Kim et. al.,  Nat. Rev. Elect. Eng. 2, 835-845, 2025

With the rapid acceleration of the digital transformation era, the continued miniaturization of electronic devices has led to an unprecedented increase in device density and interconnect complexity, thereby driving the demand for high-speed data storage, processing, and communication within increasingly compact form factors [1,2]. At the same time, the rapid expansion of artificial intelligence (AI)-enabled space technologies is accelerating the adoption of cost-effective commercial off-the-shelf (COTS) electronic devices in radiation-rich environments [3]. In particular, neuromorphic computing, which integrates data storage and processing within a single device, has emerged as a promising solution for efficient AI computation in space systems [4]. However, in such applications, radiation-induced degradation or device failure can lead to critical system-level malfunctions, making device reliability under extreme environments a key requirement.

In this study, we systematically investigate the reliability of two-dimensional (2D) material-based resistive random-access memory (RRAM) devices for next-generation neuromorphic computing in extreme radiation environments. Owing to their atomically thin structures, 2D materials are expected to exhibit enhanced tolerance to radiation-induced defect formation and charge trapping, making them a promising platform for highly durable neuromorphic devices capable of operating in harsh environments. We select Te, MoS2, and h-BN as representative active-layer materials and comparatively examine the stability, degradation behavior, and key reliability issues of each material system under radiation exposure. In addition, we discuss possible material- and device- engineering strategies to mitigate radiation-induced degradation and improve operational stability.

References

[1]   S. H. Shin. et al., Nano Letters, Mini Review, 25 (18), 7224–7233 (2025)

[2]   H. H. Yoon. et al., npj 2d materials and applications, 9 (68), 1-11 (2025)

[3]   Budroweit, J. et al., Electronics, 10(9), 1008 (2021)

[4]   F. Ortiz et al., IEEE Transactions on Machine Learning in Communications and Networking, 2, 169-189 (2024)

As silicon scaling approaches its fundamental limits, new materials are needed for next-generation logic and interconnect technologies. This talk presents a Te-based p-type 2D semiconductor for MoS₂-compatible CMOS integration and low-resistivity MoP topological semimetal thin films as promising candidates for future interconnects.

References

[1] S. H. Shin. et al., Nano. Lett. 25 (18), 7224–7233, 2025

[2] H. H. Yoon et. al., npj 2D Materials and Applications, 9 (1) 68, 2025

[3] H. Kim et. al.,  Nat. Rev. Elect. Eng. 2, 835-845, 2025