This study explored the effects of various configuration parameters of the Gemmini hardware accelerator framework on performance and resource utilization. The contributions of this study include the following:

• Detailing the software and hardware components generated using the Gemmini framework. This was done to make it easier to understand and implement Gemmini since the documentations have a long learning curve.

• The exploration of various GEMM dimensions and dataflow options on different configurations of the Gemmini accelerator is reported to measure performance metrics under various configurations and workloads.

• Mapping the generated register transfer level (RTL) code of various Gemmini configurations on a field programmable gate array (FPGA) device to extract synthesis results, such as area, frequency, and power.

• Demonstrating the effects of various Gemmini configuration options on performance and hardware resource utilization metrics.

Funders: This work was supported by the Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean Government (MSIT) (no. 2022-0-00394, Development of AI semiconductor for level 4 self-driving based on functional safety).

Duration: December 2022 - February 2023

Collaborating Institutions: 

• CSIR-Institute for Scientific and Technological Information (CSIR-INSTI)

• Korea Electronics Technology Institute (KETI)