Lab 7. (Thunderbird Tail Lights)
(Israel Sanson, EE, TCES 230 Digital Logic
Embedded Files
Introduction
Introduction
Our goal for this lab is to gain knowledge and experience in designing finite state machines, our objective is to build a Moore machine that controls the Thunderbird taillights, which has a sequence that it must follow, in order for it to be functional. We will complete this task by, using the current and next state tables, that we will create, then we will be using web-based tools to minimize functions and aid in designing the circuit, this also include using commands not known before in Logisim to aid in the building of the circuit. After this is all completed, and 100% working, we will be using model Sim to code and simulate the circuit as well, to test the functionality of the circuit.
State Machine Design
State Machine Design
To begin the design of this Moore machine, we have to look at the problem statement, which it states the sequence of the lights and when R=1 or L=1 a specific sequence of lights should turn on. When L=1 a sequence of 3 lights will turn on La, Lb La, LcLbLa; same goes when R=1 and all light flash all together when H=1. In order to complete this task, I designed an 8-state diagram, setting IDLE/S0 as the reset, L1=S1, L2=S2, L3=S3, R1=S4, R2=S5, R3=S7, H=S7, representing the lights and sequence when L=1 and/or R=1 and/or H=1. I represent the current values with variables ABC, to represent the 8 states; then I configure the next state with all the possible inputs of L, R&H. Furthermore, I add another table to represent the next state of the of the output, when a certain input is put into the system. In the table you will notice 2 of the input sequence are all do not care cases, originally from the problem statement it stated L cannot =1 when R=1 and vice versa, that's why we set those as do not care cases. Using both tables, and the way I set it up, I was able to identify the outputs of the system. I was then able to use the tables to create a 64-bit next state table, seen at Table 1-0, which I used to input the data into the table from the logic expression tool website, which generated the equations I needed to build the next state circuits on Logisim. After a few failed attempts, I was able to successfully build the circuit in Logisim. I began by testing the circuits output and comparing the output to the next state table with all 64 combinations to make sure it ran correctly. Analyzing the output data to the table I confirmed that it ran correctly, I did this by using the input buttons to create the combinations from the table, and the data from the table and simulation matched. I connected the 3 D flip flops, using the output from the flipflops and connecting them to the next state circuits. I used the output table to create the output logic from the expressions that were composed using the logic expression tool. I tested the functionality of it once I connected them to the flip flops. Using a synchronous clock at 2Hz, I ran the simulation to analyze the sequence of the lights when L=1, and starting from La, the lights ran in perfect sequence, La, LaLb, LaLbLc, then reset to off and run the sequence again, as long as L=1, or the left blinker is activated in the thunderbird; I then ran a final test for L=1 to confirm its functionality, I switched H on to see if it would go to idle then run its sequence, which it ran smoothly, turning all the lights on and off simultaneously. Also, when the signal switches from L to R at any point of the sequence it goes to idle first as it should. Therefore, that problem has been solved, at least for the left signal. Furthermore, I ran a simulation for R=1 and the signal ran correctly, Ra, RaRb, RaRbRc, then resets and starts over again, as long as R=1, I then tested to see if the lights go to idle when L=1/R=0 and H=1, while observing the sequence I confirmed that it did; additionally when H=1 no matter what R or L equal, H takes precedence, which it did and ran as it should, lights on and off simultaneously till H=0. Lastly, when all equal 0, it stays at Idle state.
Table1-3: This is the current and next state table I used to create Table 1. I explained above how I came up with this table.
Figure 1-2: I put IDLE in the middle, since everything has to go back to idle when transitioning directions or running a sequence. I was thinking we have one left signal with 3 possible combinations that run as a sequence as long as the input remains at 1. Also showing that when transitioning to a new direction, all must go to idle state, and setting H as the one that takes precendence.
Table 1-0: 64 possibilities with 3 outputs, this information was used to create the next state logic expressions for the circuits.
Ak+1= ~A~B~C H+~A~B~C R+A~B R~H
Bk+1=~A~B~C H + ~A ~B C L ~H + ~A B ~C L ~H + A~B C R ~H
Ck+1= ~A ~B ~C H +~A~C L~H + A~B ~C R ~H
Table 1-1: This the table representing the output of the left and right signal. La=~AC+~AB+BC, Lb=~AB+BC, Lc=BC. For Ra=A, Rb=AC+AB, and Rc=AB. These are the resulting expressions from the table. I input these expressions into Logisim and created the output circuits that the lights connected to.
Logisim Simulation.
Logisim Simulation.
I set the inputs as A B C L R H, the outputs An, Bn, Cn representing the next state, I used the generated expressions from the table using the logic expression tool, once created I tested the output, and I compared the data to the table the simulation outputs matched the table. Once I connected the 3 D flip flops to the circuits, and the output circuits; I used lights as the outputs to represent the signal sequence from a thunderbird. I ran the sequence and compared the data to the outcome that the problem originally stated, and the output matched perfectly with the desired outcome, which is a simulation of a turn signal from a thunderbird. When L=1 the circuit ran the sequence, La, LaLb, LaLbLc, then back to idle, repeating the sequence again; I tested if the H took precedence, and it did at all possibilities during the sequence that its currently running, no matter what it went to idle then ran the hazard light sequence. I compared my observations from the simulation against my tables and the current and next states matched.
Figure 1-1: Next state circuit, I tested the output of the circuit with the different combinations from the table, and the circuit is true. The next state output is connected to the input of the D flip flop.
Ak+1= ~A~B~C H+~A~B~C R+A~B R~H
Figure 1-2: Next state circuit for Bn, output matched the next state table on Table 1-0. All possible combination of inputs from the table to observe the output of the circuit, to check if it was one when it was supposed to.
Bk+1=~A~B~C H + ~A ~B C L ~H + ~A B ~C L ~H + A~B C R ~H
Figure 1-0: The circuit answered the problem statement, when R=1, the right light sequence begins as previously stated, then resets, all lights off, and begins again, until otherwise. Because R and L can never =1 simultaneously, I turn it off and input L. The sequence is correctly ran as previously stated then it resets and begins again. When switching to H=1 while either sequence is running, no matter at what state of the sequence is at, it resets to idle then begins the hazard light sequence, which is on and off simultaneously.
Ak+1= ~A~B~C H+~A~B~C R+A~B R~H
Bk+1=~A~B~C H + ~A ~B C L ~H + ~A B ~C L ~H + A~B C R ~H
Ck+1= ~A ~B ~C H +~A~C L~H + A~B ~C R ~H
La=~AC+~AB+BC,
Lb=~AB+BC,
Lc=BC.
For Ra=A,
Rb=AC+AB,
and Rc=AB
Figure 1-3:
Next state circuit for Cn, output matched the outputs from Table 1-0.
Ck+1= ~A ~B ~C H +~A~C L~H + A~B ~C R ~H
Figure 1-4:
Output logic gates, when they are connected to the flip flops, and the clock runs, the sequence follows the tables and the desired outcome, with all possible inputs.
La=~AC+~AB+BC,
Lb=~AB+BC,
Lc=BC.
Ra=A,
Rb=AC+AB,
Rc=AB
ModelSim Simulation.
ModelSim Simulation.
When coding Verilog, my thought process for building the code was to assign the expressions that were generated from the logic expression tool. I assigned the next state output as An, Bn, Cn, with their appropriate expressions seen in the table1-0. I assigned the An, Bn, Cn, Lc, Lb, La, Ra, Rb, Rc as the outputs, also assigning the flip flop outputs as well. I also used the assign feature in Verilog to assign the expressions for the output gates. I then created a wire for all the outputs excluding the flip flop outputs. Then in the test bench I added over 70 instances to show if the lights were functioning correctly. Analyzing the timetable, when R=1, L=0, H=0 we can clearly see that the sequence begins with Ra, continues to RaRb, RaRbRc, the back to idle state, 000, following the timetable when L=1, R=0, H=0, it followed the sequence correctly, La LbLa LcLbLa. When H=1 no matter the state, unless its already in idle it goes back to idle then the sequence begins all outputs turn on and off simultaneously. Lastly, I used the current and next state table to compare with the timetable, analyzing the data, the next states matched and the inputs and outputs as well matched the data.
Conclusions
Conclusions
Running the simulation on Logisim helped me get a better grasp at understanding the process of a D flip flop. Setting an output in Logisim to see how the value waits there before the clock turns again, then seeing the value passed through on the next rising edge of the clock. Building the Moore machine was challenging but rewarding, being able use the tools in a more efficient way to create circuits and create expressions, expanded my knowledge in the inner workings of state machines. Using the logic expression tool made the process of creating tables and getting the Boolean expressions from them; being able to expand the functionality of Logisim by using the analyze circuit option broaden the capabilities of the software. Using these as aids made the process more efficient, with minimal possible errors from miss calculations and mistakes that can be made when dealing with a 64-bit table. Creating the code for the circuit using the new methods that we learned from the videos made writing the code more efficient, less are for mistakes, but if there are mistakes, they can be identified faster, using the assign command. Lastly, I was able to gain a deeper understanding in the intricacies of Moore machines, through creating the expressions, to running the simulations on Logisim and Verilog, using additional tools from the software to efficiently build circuits.
Appendix: Verilog code:
/*
* Module for 3-bit counter
* Author: Israel Sanson
*/
module thunderbird(clk,clear,L,R,H,An,Bn,Cn,A,B,C,Lc,Lb,La,Ra,Rb,Rc);
// Declare inputs and outputs
input clk,clear,L,R,H;
output A,B,C,An,Bn,Cn,Lc,Lb,La,Ra,Rb,Rc;
//
// Declare internal wires
wire An,Bn,Cn,Lc,Lb,La,Ra,Rb,Rc;
// declare six D flipflops to store values
dff dff_A(An,clk,clear,A,A_bar);
dff dff_B(Bn,clk,clear,B,B_bar);
dff dff_C(Cn,clk,clear,C,C_bar);
//dff dff_D(Dn,clk,clear,D,D_bar);
//dff dff_E(En,clk,clear,E,E_bar);
//dff dff_F(Fn,clk,clear,F,F_bar);
// Next state logic, starting with LSB
//assign Fn = F_bar; // Or ~F
//assign En = E^F;
//assign Dn = D^(E&F);
assign Cn = (~A&~B&~C&H)|(~A&~C&L&~H)|(A&~B&~C&R&~H);
assign Bn = (~A&~B&~C&H)|(~A&~B&C&L&~H)|(~A&B&~C&L&~H)|(A&~B&C&R&~H);
assign An = (~A&~B&~C&H)|(~A&~B&~C&R)|(A&~B&R&~H); // A is MSB
//Assign flip flop outputs
assign Lc = (B&C);
assign Lb = (~A&B)|(B&C);
assign La = (~A&C)|(~A&B)|(B&C);
assign Ra = (A);
assign Rb = (A&C)|(A&B);
assign Rc = (A&B);
//
endmodule
module thunder_tb();
reg clk,clear,L,R,H;
wire A,B,C,Lc,Lb,La,Ra,Rb,Rc,An,Bn,Cn;
thunderbird tgl (.clk(clk),.clear(clear),.L(L),.R(R),.H(H),.A(A),.B(B),.C(C),.An(An),.Bn(Bn),.Cn(Cn),.Lc(Lc),.Lb(Lb),.La(La),.Ra(Ra),.Rb(Rb),.Rc(Rc));
initial begin
// start with clear low to reset flip flops
// The only input variable needed for a counter is the clock. Needs 64 cycles though so copy and paste!
clk = 0; clear = 0; H=0; L=0; R=0; #10;
clk = 1; clear = 1; H=0; L=0; R=0; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; H=0; L=0; R=1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; H=0; L=1; R=0; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; H=1; L=0; R=0;#10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; H=0; L=0; R=1;#10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; H=0; L=1; R=0;#10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; H=1; L=0; R=0;#10;
clk = 1; #10;
clk = 0; #10;
clk = 1; #10;
clk = 0; #10;
end
endmodule
module dff(d,clk,clear,q,q_bar);
// inputs and outputs -- note that this flipflop has clear but not preset. clear to reset fliflops
input d,clk,clear;
output q, q_bar;
// internal signals
wire n1,n2,n3,q_bar_n;
wire cn,dn,n4,n5,n6;
// First Latch
not (n1,d);
nand (n2,d,clk);
nand (n3,n1,clk);
nand (dn,q_bar_n,n2);
nand (q_bar_n,dn,n3,clear);
// inverter on the clock
not (cn,clk);
// Second Latch
not (n4,dn);
nand (n5,dn,cn);
nand (n6,n4,cn);
nand (q,q_bar,n5);
nand (q_bar,q,n6,clear);
endmodule
Report abuse