Lab 5. (MUX, DEMUX, and Latches)

(Israel Sanson, EE)

TCES 230 Digital Logic

Introduction

In lab 5 our goal is to continue to gain experience in building circuits and simulating them, digitally on Logisim and model Sim using Verilog. Our objective is to be familiarized with 2-1 multiplexers and 1-2 demultiplexers and latches. Another outcome of this lab is for us to build and test circuits individually and then connect them together to test the larger circuit.

Prelab-Part 1

I built a 2-1 multiplexer in Logisim and connected it to a 1-2 demultiplexer. Three inputs from the 2-1, a select bit S and x0 and x1, with 8 possible cases. Truth table matches Logisim, I built the circuit on Logisim first then created the truth table. All possible outputs matched the truth table from Table 1-1. The Demultiplexer was built using Boolean algebra, which was x0=s_not,f and x1=s,f seen on figure 1-7. I used two AND gates and followed the expression, which then its matched with Table 1-3 following the same output outcomes. Lastly, I connected the output of the MUX to both AND gates from the 1-2 DEMUX and connect the select bit output to the 2-1 select bit as seen on figure 1-6. Testing the low and highs against the truth table, the outputs match. When I coded the MUX and DEMUX in Verilog, I just declared all the Nand gates needed, while following the Logisim schematic I connected to the output of the 2-1 with the inputs of the 1-2. I declared 2 inputs and D, and En, and the all the gate outputs and actual outputs. I tested 8 cases starting the En being on for the initial condition. When running the code and analyzing the time table, we get the same outputs when compared to the truth table and digital circuit.

Table 1-0:

Timetable of my 2-1 and 1-2 multiplexer connected to a demultiplexer that was created using Verilog on model sim. When comparing to the truth table from figure 1-3 and the digital circuit on Logisim (figure 1-6) it confirms that the mux and demux are working properly; comparing the input and output, I get the same outcome as all three. When X1 and f has high voltage the output is true for Y1 and for we can see high voltage for Y1 when x1 is 1 and x0 and f are false; and another instance when x1 and x0 are both 1's and S is 0, we get a true output

Table 1-1: Truth table for a 2-1 MUX connected to a 1-2 DEMUX. This table was built using all 8 possible inputs with and 2 outputs. When building the digital circuit and comparing the output from Logisim and this truth table, we see matching numbers.

Figure 1-6: Digital circuit build on Logisim, 2-1 MUX connected to a 1-2 DEMUX. We can see that its built correctly because, when x0 and x1 are true, we get an output of 1 in Y0, and following the truth table, all outputs match.

Figure 1-7: 1-2 DEMUX. When f is 1 and S=0 we get an output of Y0. But when both have are true, we get an output of Y1.

Table 1-2: Truth table of a 2-1 MUX, when testing the input and output values against this truth table using Logisim (figure 1-8), we observe that the values are equal to this truth table for all 8 cases.

Table 1-3: Truth table of a 1-2 DEMUX, accurate to Verilog, and Logisim.

Figure 1-8: Logisim digital circuit of a 2-1 MUX. All possible input and output outcomes match truth table, and verilog code.

Prelab-Part 2.

I built a d latch on Logisim, when analyzing the digital circuit we get errors for the output, we must enable En for our circuit to work. When enabling we see that Q_not is true, and this only works if enable is one if initially D was to turn on the nothing would happen until enable was true. Now when turning En off, we observe that Q_not stays on, and turning either D or En on, we do not get any change. It's not until both D and En are true that the output changes to Q, then it holds that value Q once you turn off enable then D; we can see that when turning D off and on, the output does not change, not until enable is turned on that the value of the output is changed to Q_not. The circuit followed the truth table, for example, it didn't matter what D was while En was on that value Q held either way. Comparing my truth table, timetable, and Logisim circuit, we observe that they all match, the same example I just gave can be said about the timetable as you can see below, D is 0 En is 1 and Q_not is true just like the truth table. When creating the code for model Sim on Verilog, it was very simple, I followed the Logisim circuit, declared 4 Nand gates set the inputs and outputs exactly as you see it below and ran the code, the only part that threw me off was having to set En initially as 1 so no errors would show up, and I ran it for 8 cases for better analyzing the data.

Figure 1-0: D latch, I followed the same procedures as explained above, and confirmed that the D latch was functioning as it should. The output was stored when both En and D were true and held when En is false no matter what D is, just like the truth table.

Table 1-0: This is the table I used to check with Logisim and Verilog.

Figure 1-1: Timetable from Verilog, when analyzing the data with all resources, we can conclude that the circuit ran as it should. I found this out by comparing it with all my resources seen in this lab.

Lab Part 1.

Our 2-1 MUX, when analyzing our built 2-1 MUX, we observe that there is no output when x1 is true and x0 and s are false, we get no output, we only get high output if x0 is one whether they are all false or true, we will get a high output. When the DEMUX is connected to the MUX, we observe the circuit behaving the way it's supposed to, comparing it to the truth table, time table, and Logisim, we conclude that circuit is working, for example, when x1 and S are both true while x0 is false we observe that Y1 gets a high output, and when x0 and x1 are true while s being false we get a high output for Y0, when analyzing all the data we see that its correctly built.

Figure 1-0: 2-1 MUX, built using the Logisim digital circuit, we concluded that this circuit is of correct configuration due to the fact that it follows all figure and tables, proving it works correctly.

Figure 1-1: 2-1 MUX attached to a 1-2 DEMUX, using the schematic from Logisim, I connected it just like the one from pre-lab part 1, they share a select bit and the output f is attached to the inputs of both AND gates. Givin me the outputs similar to those from the truth tables and digital circuit.

Lab Part 2.

We built a D latch using and inverter and one Nand gate chip, after it we built it, we tested it using our truth table against the LEDs on the circuit that acts as the output, so we know we are doing things correctly. We tested it by turning on enable then turning on D and turning off En to see if the value held, which it did, just like the other resources used to create the D latch. When turning off enable first then D, the new value holds and no matter what D is, that value is held until enable is turned back. Therefore, we can conclude that our circuit was built correctly, due to the comparison of my other resources and the outcome that I just explained. Finally, after we connected our MUX to the D latch, we can conclude that the 2 values are held with the same logic for the MUX and DEMUX. Initially 1 bit of memory is held but when connecting the mux, we can observe that 2 bits of memory can be held as seen below.

Figure 1-0: D latch built on bread board. Circuit provided the same outputs from the Logisim, truth table, and timetable.

Figure 1-1: MUX and DEMUX attached to D latch. Looks to me that it holds two bits of memory.

Conclusions

In conclusion, more experience was gained using the Verilog, Logisim and building circuits. We simulated multiple circuits and tested them to gain knowledge and experience using gates by simulating them and building them physically. Also, our objective was achieved, we became familiar with multiplexers and demultiplexers, I gained a real understanding on how circuit schematics can be translated using Verilog, truth tables, and other resources to verify that our data is correct. Finally, I was expecting to get a better understanding on D latches and the idea of a gate holding a value, which I could not comprehend on paper, but when seen physically, I understand now the idea of holding, or storing memory of a value.

Appendix: Verilog code for dlatch, and mux and demux

module testgates(D, En, Q, Q_not, not_out, nand_out, nand_outb);

// declare inputs and outputs

input D, En;

output Q, Q_not, not_out, nand_out, nand_outb;

// declare an inverter---note: output HAS TO go first,

not(not_out,D);

//not(not_a,a);

nand(nand_out, D, En);

//declare an NAND gate

nand(nand_outb, not_out, En);

// third nand gate declared

nand(Q,nand_out,Q_not);

nand(Q_not, nand_outb, Q);

// declare an OR gate

//or(or_out,a,b);

endmodule

// this is a testbench file for testgates.v, send variables to testgates

// Author: Israel Sanson

module testgates_tb();

// inputs that we send to testgates() are called registers

reg D, En;

// outputs that we receive from testgates

wire Q, Q_not, not_out, nand_out, nand_outb;

// create an instance of our main module testgates

testgates tg1(.D(D),.En(En),.Q(Q),.Q_not(Q_not),.not_out(not_out),.nand_out(nand_out),.nand_outb(nand_outb));

// specify our teste cases for this test gates module

initial begin

//case 1

D=0;En=1;#100;

//case 2

D=0;En=0;#100;

//case 3

D=1;En=0;#100;

//case 4

D=1;En=1;#100;

//case 5

D=0;En=0;#100;

//case 6

D=0;En=1;#100;

//case 7

D=1;En=0;#100;

//case 8

D=1;En=1;#100;

end

endmodule

// this is a testbench file for testgates.v, send variables to testgates

// Author: Israel Sanson

module testgates_tb();

// inputs that we send to testgates() are called registers

reg x0,x1,s;

// outputs that we receive from testgates

wire not_out,not_out2, and_out, and_out2,f,y0,y1;

// create an instance of our main module testgates

testgates tg1(.x0(x0),.x1(x1),.s(s),.not_out(not_out),.not_out2(not_out2),.and_out(and_out),.and_out2(and_out2),.f(f),.y0(y0),.y1(y1));

// specify our teste cases for this test gates module

initial begin

// Specify our test cases for this testgates module

// Case 1: Select the first input (x0) when s=0

x0=0; s=0; x1=0; #100

// Case 2: Select the second input (x1) when s=1

x0=0; s=0; x1=1; #100;

// Case 3: Select the second input (x1) when s=1

x0=0; s=1; x1=0; #100;

// Case 4: Select the second input (x1) when s=1

x0=0; s=1; x1=1; #100;

// Case 5: Select the second input (x1) when s=1

x0=1; s=0; x1=0; #100;

// Case 6: Select the second input (x1) when s=1

x0=1; s=0; x1=1; #100;

// Case 7: Select the second input (x1) when s=1

x0=1; s=1; x1=0; #100;

// Case 8: Select the second input (x1) when s=1

x0=1; s=1; x1=1; #100;

//case 1

//x0=0;s= 0;x1=1'b00;#100;

//s=y0;

//case 2

//x0=0;s=1;x1=1;#100;

//s=y1;

end

endmodule

module testgates(x0,x1,s,y0,y1,not_out2,not_out, and_out, and_out2, f);

//2-1 MUX

// declare inputs and outputs

input x0,x1,s;

output not_out,not_out2, and_out, and_out2, f, y0, y1;

// 2-1 MUX

// declare an inverter---note: output HAS TO go first

not(not_out,s);

//not(not_a,a);

and(and_out,not_out,x0);

//declare an NAND gate

and(and_out2,x1,s);

// or gate declared

or(f,and_out,and_out2);

// 1-2 demux

and(y0,f,not_out2);

and(y1,f,s);

not(not_out2, s);

// declare an OR gate

//or(or_out,a,b);

endmodule

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