Lab 4. (Voter Circuit)

(Israel Sanson, EE)

TCES 230 Digital Logic

Introduction

My objective is to design and build a digital circuit that will act as a voting machine, the objective of this laboratory assignment is to allow me to gain experience in the laboratory, using the equipment, and to gain knowledge in testing digital circuits. We will also be gaining experience in using only NAND gates to build our circuit and using Model Sim to practice simulating circuits.

Prelab

In the pre laboratory assignment 4, I will be designing and building a logic circuit that will be implemented as a way to vote for the restaurant to eat at using 0's and 1's as the options. The digital circuit will be able to choose the restaurant that everyone will eat at, using the algorithm given from the instructions. I will build the truth table and make the circuit in Logisim, then I will simulate the circuit in Model Sim using Verilog. When creating the truth table, I put a 1 anywhere there were three 1's and anytime the input J1 and J2 were both true then the output was true. I used a kmap to simplify the expression and built the digital circuit in Logisim with the same outcome from the truth table. When writing my code, I decided to declare 4 NAND gates, with 4 inputs and 4 outputs. I followed my Logisim circuit and connected the inputs to the proper Nand gates, then connecting all the Nand gate outputs to the last Nand gate as inputs, resulting with our final output value. For the testbench I added 4 inputs to the register, keeping the variables the same as the testgates file which made it easier to create our instances; I then assigned the outputs to a wire, also creating 16 different cases for my inputs and outputs. The code was able to compile, and I was able to simulate the circuit and the timetable created, followed the truth table as expected, it gives a true output with the given algorithm, when a and b are true output is true and when any 3 inputs are true then the output is true, otherwise false including when it's a tie. Comparing the data with my truth table, digital circuit and timetable, following the instructions from the prelab, I was able to create a working voter circuit that will choose which restaurant to eat.

Figure 1-0:

Kmap and equation used to design and build digital circuit.

Table 1-0:

Truth table created using the information given in the word problem. There will only be a true output, given certain conditions which are either J1 and J2 are true, or any 3 inputs are true. False otherwise, including ties.

Figure 1-2:

Digital circuit built, based of Table 1-0. 4 total NAND gates used with 4 inputs. When J1 and J2 are true or any 3 inputs are true the output will be true. When a tie occurs, the output will be false.

Table 1-2:

Time table created from my code in verilog. Comparing the time table to my truth table and my logisim digital circuit, the results are as expected. The output of the time table follows the truth table and the circuit built digitally and physically..

Part 1.

In the lab portion I built a circuit based of my digital design. I first approached the built by going down the inputs and connecting them to their proper 2 input or 3 input NAND gates, which was not the best approach since I ended confusing myself and I was not getting the correct output, the led's stayed on. I restarted, but this time I used specific colors for the jumps. I first connected the 3 NAND gate outputs just like the circuit in Logisim, then I started connecting the switches to the proper NAND gate inputs. This time I succeeded and getting the outcome I wanted, and I tested my truth table with the circuit by using an LED, turning the J's on only gave me a true output, and turning any 3 inputs on gave me a true output, and finally any ties excluding the J's gave a false output.

Figure 1-0:

Circuit built using 2 NAND gates, one with 2 inputs and the other with 3 inputs. I included a 4 input switch to be abe to test the truth table information.

Conclusions

Using the equipment has been one of the biggest challenges for me, but as time has passed, I feel like I'm becoming more familiar with the equipment, also building circuits and reading the data sheets for the gates being used becomes easier to do. I'm feeling more comfortable with model Sim and using Verilog. Being able to create a truth table, then capture the expressions using kmaps and Boolean algebra; to get an expression that will be used to create a digital circuit in Logisim, and then translate that information into Verilog to simulate a truth table, allows me to compare my data. Therefore, being proficient in the equipment helps me get accurate data for me to analyze and compare with the truth table and digital circuit built in the prelab. Finally, when building the circuit on the bread board it reinforced that my data and approach was accurate. Using 4 switches as the inputs and an LED as the output to simulate the truth table that I created, and the timetable created on Verilog.

Appendix-Verilog Code:

// this is a testbench file for testgates.v, send variables to testgates

// Author: Israel Sanson

module testgates_tb();

// inputs that we send to testgates() are called registers

reg a,b,c,d;

// outputs that we receive from testgates

wire NAND_OUT,NAND_BOUT,NAND_COUT,NAND_all;

// create an instance of our main module testgates

testgates tg1(.a(a),.b(b),.c(c),.d(d),.NAND_OUT(NAND_OUT),.NAND_BOUT(NAND_BOUT),.NAND_COUT(NAND_COUT),.NAND_all(NAND_all));

// specify our teste cases for this test gates module

initial begin

//case 1

a=0;b=0;c=0;d=0;#100;

//case 2

a=0;b=0;c=0;d=1;#100;

//case 3

a=0;b=0;c=1;d=0;#100;

//case 4

a=0;b=0;c=1;d=1;#100;

//case 5

a=0;b=1;c=0;d=0;#100;

//case 6

a=0;b=1;c=0;d=1;#100;

//case 7

a=0;b=1;c=1;d=0;#100;

//case 8

a=0;b=1;c=1;d=1;#100;

//case 9

a=1;b=0;c=0;d=0;#100;

//case 10

a=1;b=0;c=0;d=1;#100;

//case 11

a=1;b=0;c=1;d=0;#100;

//cas 12

a=1;b=0;c=1;d=1;#100;

//case 13

a=1;b=1;c=0;d=0;#100;

//case 14

a=1;b=1;c=0;d=1;#100;

//case 15

a=1;b=1;c=1;d=0;#100;

//case 16

a=1;b=1;c=1;d=1;#100;

end

endmodule

module testgates(a,b,c,d,NAND_OUT,NAND_BOUT,NAND_COUT,NAND_all);

// declare inputs and outputs

input a,b,c,d;

output NAND_OUT, NAND_BOUT, NAND_COUT,NAND_all;

// declare an inverter---note: output HAS TO go first

//not(not_a,a);

nand(NAND_OUT,a,b);

//declare an NAND gate

nand(NAND_BOUT,a,c,d);

// third nand gate declared

nand(NAND_COUT,b,c,d);

nand(NAND_all,NAND_OUT,NAND_BOUT,NAND_COUT);

// declare an OR gate

//or(or_out,a,b);

endmodule

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