Lab 3 The half adder
(Israel Sanson, Electrical Engineer)
TCES 230 Digital Logic
Embedded Files
Introduction
Introduction
In this prelab we will first, be learning how to use Model Sim software to code in Verilog. We will have to decipher the question first then create truth table using the carry sum method in order to create our truth table. After, I will translate that truth into Logisim, to create a digital circuit. This circuit will be constructed using a full adder and a half adder to get a simulation of our results. Then for the actual lab we will be building a half adder, which consist of an AND and a XOR gate, on the breadboard.
Prelab
Prelab
In the prelab I added binary numbers using the carry sum method to create a truth table for my digital circuit. I then used kmaps to get my equations and converted them to xor gates after simplifying them. For the s2 output, I was not getting any inverted equations, so I looked up a video and used the method I saw, which was to evaluate 1's by themselves instead of trying to get the biggest group, in order to get the equations that I needed to convert them in to xor gates. I then used my Boolean algebra answers to create my half adder and full adder on Logisim. The built circuit output the correct outputs from the truth table which confirmed my equations and outputs from the truth table.
Figure-1:
This image shows the truth table I created, and the kmaps that helped create my circuit in Logisim. You can see that I used Boolean algebra to make my xor equations so that I could build a half adder and a full adder.
Figuire-2:
Here we have my full and half adders that I built in Logisim, running the simulation, it followed the truth table, as expected, getting the same outputs, when simulating the inputs from the truth table.
Figure-3:
This is the code that I wrote in ModelSim . This a representation of a half adder. I used your video, and multiple videos on YouTube to help create this code.
Figure-4:
This is my Bench code from ModelSim. Used to run the simulation.
Figure-5:
Half adder code, using videos from youtube to create this code.
Figure-6:
2 bit adder code. I assigned the adder to the module, with the input first and output last, I assigned a wire because it looked right, since I only learned how to do this from a 20 minute video.
Table-1:
Timing table from model sim. When compared to my truth my timing table was off. So most likely I made mistake in the code which affected my timing table.
Part 2.
Part 2.
When building the half adder with an AND in the bottom, and a xor gate at the top with 2 inputs, we can see that when the switch is off but one is on we get a true output for the sum, and a false output for the carry, its not until both ouputs are true that we get a true output for the carry. Since we were just testing the Half adder to get familiar with it, we can see from the truth table that it works as expected.
Table-1:
The truth table for a half adder that we built. As you can see, it is similar to outcome of our built circuit. Ensuring that our circuit is correctly built.
Figure-1:
three images of the circuit we built in lab 3. Here we have two switches top and bottom, connected to an AND gate, and the same two switches controlling the xor gate. LED lights are there to show that there is powe in the swith and the other 2 led lights located at the xor and AND gate outputs, to have visualization of our truth table. Outputs for the gates with led means true or 1 when on, false or 0 when off.
Conclusions
Conclusions
In conclusion, the lab was challenging this time, using the Verilog was one of the most difficult parts. It was a great learning experience, because I could not wrap my head around the idea of half and full adders. Creating the truth table, kmaps and Boolean algebra was helpful when trying to write the code. Since this lab was a quick one, and we were gaining experience and knowledge by physically seeing how a half adder works, I can that the half adders in the real world when compared to the truth table, we can see that it does exactly as the truth table says. We were able to proof this by using LED's to in the switch and the outputs for the half adder, so we could physically see it.
74ls00-datasheet-1024x576.jpg (1024×576) (circuits-diy.com)
74LS266_1.PNG (276×205) (bp.blogspot.com)
(14) Tutorial 1: Verilog code of Half adder in structural level of abstraction - YouTube
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