Lab 6. (Designing counters)
(Israel Sanson, EE)
TCES 230 Digital Logic
(Israel Sanson, EE)
TCES 230 Digital Logic
There are three objectives for lab assignment 6, the first objective is to gain an understanding in designing counters, by using Logisim to design and test the counters built; not only are we looking the gain an understanding in counters but also flip flops. Through, Logisim, testing and designing counters with flip flops we will be gaining knowledge for a better understanding on flip flops. Additionally, we will build and simulate 4 bit counters in Logisim, so that we can test them and observe the way the work. Lastly, we will gain experience and knowledge after our last objective, which is to build a 4 bit counter, but this time using JK flip flops and using a bread board to see it in real time.
I created a 4-bit counter using D flip flops with a clock as the only input and four outputs. Each D flip flop represents one bit, I connected the output of each flip flop to the input of an AND gate and XOR gate, Q0 is the LSB and Q3 is the MSB. I added an initial condition which Q0 is initially 0 and an input z always on, to allow the counter to go through the sequence and reset itself back to zero. Building the circuit, I found that you can't just use D flip-flops, you have to add gates to get the correct results of the 4-bit counter. Running the simulation, and analyzing the data, we can conclude that the set up is correct, the counter runs its course starting at 0000, then 0001 and so on until it runs through all 16 cases.
Figure 1-0: D flip-flop using AND gates and XOR gates, to allow the counter to go through the sequence. Analyzing the date, it follows the next count table I created.
Table 1-0: Current state and next state table that links both of these values.
I built a 4-bit counter using JK flip-flops, all the JK inputs are attached to an enable, which is always on, the clock then simulates the JK flip flop 4-bit counter, observing the counter from msb to lsb, it follows the current and next state table, with it starts with 0000, then 0001, 0010 all the way to 1111, to which its next state is 0000. No additional gates were needed, for the design of the JK flip-flop 4-bit counter, correct operation was verified, using LEDs to simulate the counter starting at 0000 going through 16 sequences.
Figure 1-0: 4 bit counter using JK flip-flops, MSB and LSB labeled appropriately. Originally the counter was counting down, I had to change the configuration of the clock and output placements ensuring correct operation. It counts from 0000 to 1111 and back to 0000.
We used my 4-bit counter built in Logisim, we used 2 chips containing 2 JK flip-flops each, for a total of 4 JK flip-flops used. Just like the schematic on Logisim we built the circuit, once built we made sure to connect the preset and clear in the chip to voltage so the counter can work correctly. Observing the flip-flop, we see that the 4-bit counter is working correctly, meaning it follows the sequence starting at 0000 all LED's off then proceeds to count up 0001 meaning only the one LED is on which is the LSB; all the way to 16 then it resets. Analyzing the counter, the voltage goes from 0V to 5V at a frequency of 1Hz, using the ac generator as the clock.
Figure1-0: Circuit built using 4 JK flip flops, each chip contains 2 JK flip flops.
Figure 1-1: Counter built using the JK flip flop design from Logisim. We used my design, and during the simulation I noticed the counter was working correctly. It starts at 0000, all the led's off, and the lights turned on and off just like the counter built on Logisim. As the clock ran aka the generator, oscillating from 0V to 5V the LEDs turned on at the appropriate time going through the 4-bit counter sequence, depending on the frequency, which we had set at 1Hz.
In conclusion, building the 4-bit counters on Logisim helped me gain an understanding in the process of designing counters using JK and/or D flip-flops. By building the D flip-flop on Logisim I was able simulate and observe the 4-bit counter going through the sequence, starting at 0000 ending at 1111, then resetting itself back to 0; dealing with D flip-flops required additional gates. For the JK flip-flop, the designing process was much simpler since it did not have any use for additional gates, to obtain the 4-bit counter that I designed, gaining the same results as the D flip-flop, but with less components. Furthermore, I was able to build the 4-bit counter with JK flip-flops, which allowed me to test the working of the circuit; using the LEDs to simulate the counter, alternating from 0V to 5V connected at the CLK, and once all the LEDs were on it resets back to zero with all the lights off. As the voltage goes from 0 to 5V, the JK flip-flops are storing that bit of memory, then when it goes back up to 5V, the next number in the sequence is stored, which in our case is an LED light; as the process continues more and more bits of memory are being stored, which once the final sequence is processed it resets, which is why the preset and clear need to connected for a correct working circuit. Comparing my observations from the main lab, with my data gained from the prelab, I can conclude that JK flip-flops can do what D flip-flops can, but with less components.