Monolithic Integration of III-V semiconductors on Silicon

Our Solution

It is possible to overcome simultaneously the issue of defects induced by lattice and thermal mismatch by partitioning the epilayer into a space filling array of prismatic III-V semiconductor crystals a few um in width by out-of-equilibrium deposition onto tall Si pillars. The finite gaps between neighbouring crystals and their faceted growth front allows for the complete expulsion of threding dislocations and other extended defects generated at the GaAs/Si interface. In addition the high aspect ratio promotes the relaxation of the thermal strain. We expect our strategy based on molecular beam epitaxy (MBE) and micron-sized silicon patterning to be applicable for the monolithic integration of a large variety of compound semiconductors.

see e.g. "Monolithic integration of optical grade GaAs on Si (001) substrates deeply patterned at a micron scale" by S. Bietti at al. Appl. Phys. Lett. 103, 262106 (2013) 

Publications

1. S. Bietti at al. Appl. Phys. Lett. 103, 262106 (2013) 

2. R. Bergamaschini et al. J. Appl. Phys. 120, 245702 (2016)

3. F. Biccari et al. Nanosci. Nanotechnol. Lett. 9, (2017).