Design and Verification of Sustainable Processes for Preventing Light Ion Contamination in MOSCAP Fabrication

My project aims to develop and document a comprehensive set of Standard Operating Procedures (SOPs) for the sustainable and safe fabrication of 4-mask NMOS transistors. These SOPs are designed to be straightforward and actionable, allowing students from EE and MATE courses to engage in semiconductor manufacturing processes actively. A critical focus of these procedures is on establishing robust cleaning protocols, which are crucial for maintaining the integrity of semiconductor environments. We emphasize the need for meticulous cleaning methods to facilitate the integration of curricula and foster student research on MEMS and solar cells. Our methodology employs MOSCAP samples as a proxy to evaluate and predict the electrical behavior of NMOS transistors, ensuring that our processes are not only theoretically sound but also practically viable. We are utilizing various analytical techniques to assess the effectiveness of our SOPs and the quality of the semiconductor devices produced. Capacitance-voltage (CV) testing, Scanning Electron Microscopy (SEM), and X-ray Diffraction (XRD) are employed to examine the electrical characteristics and material properties of the silicon wafers. This multifaceted approach ensures that the devices we develop meet both educational and research objectives, verifying their functionality and relevance to the fields of semiconductor manufacturing and device fabrication. By implementing these SOPs, we aim to bridge the gap between theoretical knowledge and practical application, providing students with hands-on experience critical for understanding the complexities of semiconductor device fabrication.