Get XSpiceHDL

XSpiceHDL_tm

Co-Simulation - Schematic Capture

Developer: Brendan Graham

_{A platform independent XSpice/Verilog Co-Simulator tool with Schematic Capture GUI functionality in-built.}

No imitations of primitive open-source ports here. Written from scratch and entirely in C++ together with the wxWidgets API, this GUI is truly professional in appearance, allowing the designer the ultimate in flexibility and simplicity! Component creation in place, right on any Schematic page, with no special OTHER screens to learn and confuse the issue! Components like net lists import and export to human readable text files. No cryptic binary serialization nonsense used! This Schematic Capture is designed for the serious Engineer who demands a flexible and configurable tool.

As functionality is added, our GUI will take on the personality of an integrated Simulation Engine. That's because XSpiceHDL has been architected from the ground up as a mixed-signal Simulator in its own right! Data types supported are Bit-Logic with Strength, Integer, Long, LLong (128-bit), Unsigned Long, Unsigned LLong, Double and Float.

Our motto: "Never have someone else do for you what you can do for yourself !"

Try out a daily snapshot below!

WARNING: This software is in Beta testing. Views of Spice derived signals and clocks within VCD waveform files may appear asymmetric with respect to Verilog derived clocks. Verilog clock cycles are by design, NOT conserved with respect to Spice simulator time. This limitation however DOES NOT restrict synchronized, cycle accurate logical-analog co-simulations. This has been done intentionally for the current release of FREE BETA testing software ONLY. Future commercial releases of ~~XSpiceHDL~~ ~~licensed product will have this restriction removed.~~

NEW: All DLL's are now Cycle Accurate!

XSpiceHDL application files:

Download the XSpiceHDL application GUI xspicehdl.zip

Download the XSpiceHDL Quick Start Manual

Note, that the Quick Start Manual assumes that the Icarus Verilog simulator is being used.

You WILL also need to download xhd_socket.dll for TCP/IP networking!

You WILL also need to download the XSpice3f5 compliant SocketNode CodeModel DLL cm_sock_ad.dll

You WILL also need to download the XSpice3f5 engine CodeModel DLL load list file DLL.lst

You WILL also need to download the modified XSpice3f5 Spice engine itself XSpiceHDL_3f5.zip

You WILL also need to download this sample Verilog netlist file xspicehdl_test_bench.v

Icarus Verilog Simulator on Cygwin files:

You MAY also need to download out XSpiceHDL SocketNode VPI DLL cm_sock_ad.vpi for Stephen Williams Icarus Verilog on Cygwin

You MAY also need to download this bash script runivlog.zip for Stephen Williams Icarus Verilog on Cygwin

You MAY also need to download our /Cygwin/project project.zip for Stephen Williams Icarus Verilog on Cygwin

You MAY also need to download our /Cygwin/home home.zip for Stephen Williams Icarus Verilog on Cygwin

You MAY also need to download our /Cygwin/iverilog iverilog.zip compilation of Stephen Williams Icarus Verilog on Cygwin

Other Verilog Simulator specific files:

You MAY also need to download our XSpiceHDL SocketNode PLI DLL SimSock_mti.pli for ModelTech ModelSim Verilog

You MAY also need to download our XSpiceHDL SocketNode PLI DLL SimSock_ncv.pli for Cadence NC-Verilog Verilog

You MAY also need to download our XSpiceHDL SocketNode PLI DLL SimSock_aldec_pli.dll for Aldec Active-HDL Verilog

Sample XSpiceHDL netlist files:

Try this demonstration XSpiceHDL GUI netlist file for Icarus smps.zip

Try this demonstration XSpiceHDL GUI netlist file for MTI smps_mti.zip

Try this sample Spice RAW (.out) waveform file: sines.out

Updated functionality and fixes:

10/02/2004

■ Fixed aliased graphics artifacts due to sloppy arithmetic in MyCanvas::DrawElement(), on mouse movement while FindElement().

■ Removed NewDevice body creation at origin by HIDING body till mouse entry onto canvas frame.

■ Optimized and removed unnecessary flicker on ruberbanded wires and component when dragging wired component.

■ FIXED ! - Block moving components and wires during (Snap to Grid = OFF) results in erroneous wire positioning arithmetic.

06/22/2004

■ Fixed just about everything imaginable and unimaginable. Co-simulation has been achieved !!!!!!!!!!!!!!!!!

03/12/2004

■ Fixed "single/multiple WIRE rubberbanding at a NODE" algorithm. WIREs would persist at their original position without dissappearing.

03/11/2004

■ Extremely significant component redraw speed modification, especially during component rubberbanding!!!!!!!!!!!

03/04/2004

■ Verilog/Spice co-simulation is now somewhat functional but ... has bugs ... lots of fleas and ticks and worms.

■ XSpice3f5 engine, independent simulation is fully functional and apparently bug free!

■ Still ZERO documentation alailable so you'll have to figure it out yourself from these notes.

■ Block move a group of schematic components, wires, lines and text by double-left-click-drag-draw-rectangular-box on the canvas, then release the mouse left button when the bounding rectangular region is appropriately sized. Next left-button-down and drag the bounding rectangle to the desired position.

■ Note: The XSpiceHDL GUI interface was developed from scratch in C++ using the wxWindows API, so as a result some GUI functions such as block move are at the moment still a bit slow. This issue will be addressed in the future.

■ Waveform viewing of Spice (binary real double) .raw and .out files if fully functional. ASCII format parsing is NOT yet available ... trivial:-)

■ The default waveform color WHITE is changeable for each waveform through a color dialogue selection box.

■ Note: The "time" waveform variable must always included in order to view waveforms.

■ If you can't figure something out, give me a call, or send an e-mail.

■ Left-double-click on a connected 2-WIRE junction will generate a NODE at the junction. WIRE junctions can then be ruberbanded.

■ Left-double-click on a WIRE will automatically remove unnecessary NODEs at WIRE endpoints.

■ Delete key deletes anything on the schematic.

12/08/2003

■ The Log window is resizable!

■ Double Left-Click on the top of the log window frame restores/minimizes the log window!

■ Left-Down on the top of the log window frame permits resizing the log frame upwards!

■Left-Down in the downward direction resets the log window to its' default size!

■ Native-mode XSpiceHDL mixed-signal simulation support is just around the corner. A couple more weeks should do it.

■ XSpice/Verilog netlisting and simulation is also nearing integration completion. All the simulation code is already completed and tested but was waiting on this GUI to be completed.

■ Scrolling the canvas (schematic window) can now be done by dragging the mouse with Left-Down. Sorry, no user configurable sensitivity adjustment yet!

■ Automatic and user manipulated schematic node cleanup implementation complete.

■ Machines' IP address is now visible on the tool-bar. The IP address of the machine hosting the XSpiceHDL executable is necessary to enable concurrent networked dynamic co-simulation among abritrary connected simulators and virtual simulations.

■ Virtual Schematic/Simulator page support is now available. Most users don't think twice about being able to switch amongst multiple schematic pages. XSpiceHDL takes this one step further! Our paging support virtual pages that can actually instantiate and represent multiple concurrent sumulations, all viewable and configurable from within a single GUI environment . . . XSpiceHDL.

■ Printer support is not yet available. :-( It's amongst the least of my worries at the moment!

■ For those interested in simulation, work has been completed on the signal-dispatch-buffers implemented as Signal-Fifo linked-lists. Each component in the design netlist hierarchy, incorporates a single instance of this buffer type. It's purpose is to store Time-Stamped-Signal Objects generated by mathematical operations on signals received at the components' Data-Inputs. The Signal-Objects are dispatched as an output when their Time-Stamp matches that of the Global-Simulation-Clock. If two or more Signal-Objects have identical Time-Stamps, then arbitration is performed. Generally however, such a situation is not permitted to occur by design.

■ Work is proceeding on the rather simple logical function operator objects meanwhile. We should be logic simulating very soon now! Mixed-signal work won't be far off though. We'll probably incorporate a direct Spice port of its functions through TCP/IP IPC, using our native simulator as a pipe. Our Simulator architecture directly supports concurrent simulators and simulations, therefore overcoming the problems associated with XSpice and other mixed-mode simulators backtracking and other nuances may easily be overcome.

■ The technique that we are using involves spawning several small time-duration simulations, thereby keeping the pipeline full in a statistically stationary sense. This is probably and intuitively the same process used in every other well performing digital system. Microprocessors and adaptive interference cancellers alike all use this same principal. The more sophisticated of these perform adaptation to a multi-dimensional performance manifold or surface. Consider the 'N' individual taps on a digital filter as being pipes, each into one of 'N' dimensions of the signal being sampled.

11/25/2003

I've lost track!!!! That's what happens when you're working at it nearly 24 hours a day. No time for documentation.

Here are some hints though:

1. Rotate and Mirror routines are in double precision arithmetic now. Use the R-ight, L-eft, and M-irror keys for transformations. Mirror axes selection are on the tool-bar.

2. Remember to turn OFF "Snap to Grid" when R-otating or M-irroring Components.

3. Mouse Right-Down on a Component or Sub-Element gets you a Component/Sub-Element Menu.

4. mport and Export netlists, including individual Schematic and Layout Components with the big I and E buttons at the right-most end of the tool-bar.

5. Auto Node generation and deletion on WIRE connections is completely functional now.

6. Manipulating and constructing a Component is now a pleasure. To place a NEW Component BODY, CLICK on the BLACK 6-pin SO-IC symbol on the tool-bar. The Component BODY is attached to the Cursor. Left CLICK on the CANVAS to place it. Right CLICK over the RECTANGLE to open it's MENU.

7. Use the D-elete key to DELETE any Component, Sub-Element, WIRE, NODE etc.

8. The CANVAS BACKGROUND is now BLACK by default. Ominous is'nt it? As it should be. That previous WHITE screen gave me a damn headache.

9. Rubberbanding of WIREs are superbe! Grab hold of a NODE to rubberband WIREs, or GRAB a Component to rubberband its connections as well.

10. You can place a NODE on a TWO WIRE connection in order to rubberband it.

Load the "example.xhd" netlist and observe!

7/19/2003

Automatic NODE insertion/deletion for >3 wire nodes functional!

Rotate component left-right functionality added!

Mirror component in horizontal-vertical axese functionality added!

Add Node to component body functionality added!

7/12/2003

Rubber-Banding support for connected wire nodes and component pin connections added and fully functional!

Automatic wire NODE insertion for drawn wires fully functional!

Algorithm enhancements to move component!

7/05/2003

Bug fix to component-sub-element-bitmap selection and motion algorithm - parent component pointer resolved for imported bitmap algorithm!

7/04/2003

Bug and algorithm fixes to component-body highlighting during mouse movement!

Bug and algorithm fixes to component-sub-element editing and element parameter stuffing during netlist-extraction!

6/19/2003

Major rectangle drawing and resizing algorithm enhancements!

Bug fixes to rectangle drawing and resizing algorithm in zoomed modes!

Deprecation of CallProcessRect() algorithm for rectangles!

6/18/2003

Resizing of rectangles now supported at the bottom-right-hand-corner!

Bitmap Overlaying of a Component Sub-Element is now fully functional!

Bitmap filename import and export to/from a netlist is now fully functional!

6/07/2003

Bitmap Overlaying of a Component Sub-Element is now partially functional!

This means that the user may now create sophisticated GUI Components composed of several impoted Bitmap Images, as well as lines, recrangles and arcs !

One can not yet save the imported Bitmap file name to an exported Netlist however, tomorrow that will be completed!

6/05/2003

Drawing, editing, and deleting of Elements (wires, lines, arcs, circles, etc.) all fully functional!

Drawing, editing, and deleting of Components and associated Sub-Elements (wires, lines, arcs, circles, etc.) all fully functional!

Several invalid pointers within line drawing algorithms resolved! Resolved with the following "pelist->DeleteContents(FALSE);"

5/31/2003

Netlist Import and Export of Components, Component Sub-Elements and Wire Nets, all fully functional!

5/29/2003

Netlist Import functionality fixed! Its fast now... just one miserable line of code!

Delete entire components and individual component sub-elements fully functional now!

5/27/2003

Netlist Import and Export functionality operaable! Import is a bit slow but will be resolved shortly.

Drawing artifacts and some major obsolete pointer dereferencing bugs fixed!

5/15/2003

Fatal memory leak fixed in line drawing algorithms.

Move Component and its sub-elements functionality added when moving the Component main body.

Removed some unnecessary clutter on the Main Tool Bar.

Will be working on Netlist Export functionality tomorrow.

5/11/2003

Append New Component Sub-Element functionality added to Component/Element right-button-down tool-menu!

One can now add lines etc, to a component parent body to form an integral electronic component symbol!

Several right-button-down tool-menu changes and additions!

Delete Parent-Component as well as Parent-Component-Sub-Elements works like a charm now!

Rright-button-down tool-menu deletion for an individual Parent-Component-body and it's Sub-Elements occurs automatically on Delete!

5/09/2003

Delete works for all Untethered-Elements, Component-Bodies as well as Component-Sub-Elements.

Untethered-Elements are Nodes. Vias, Wires, Lines and Rectangles and Circles.

Components are a collection of Component-Sub-Elements which are an integral part of a Component Instance!

Component-Sub-Elements can be Nodes, Vias, Lines, Wires, Rectangles or Circles but are integrally connected to their Mother-Component!

Added Log window to the bottom of the Schematic Capture window!

5/08/2003

Delete works for deleting Elements but not Netlist imported Components as yet, . . . tomorrow it will!

ZoomIn with ( I / i - key), ZoomOut with ( O / o - key) !

Minor fixes to the netlist import parser!

5/04/2003

Netlist import capability from text file still in elementary form, but the fundamentals are there!

Right-click on a drawn element brings up an interactive properties dialog!

Brush, Colour, Size and Client Position properties are currently interractive!

Element Types are LINE, POINT, RECTANGLE currently!

Element Brush Styles are TRANSPARENT, SOLID and a few others I can't remember right now :-)

4/30/2003

Enhanced GUI tools menu and tool selection.

Move cursor over line or wire (element) highlights line or wire.

Move cursor over node highlights node.

Move cursor over recrangle likewise.

Can draw lines with arbitrary begin and end points with one mouse click per point.

Right-click aborts all current actions including drawing lines, rectangles etc..

Can draw orthogonal lines automatically if selected.

Can generate rectangles and four line rectangular segments automatically.

Can import a bitmap as the graphic used to represent a component visually.

Can change background, wire, line color.

Can use a user drawn symbol as the components graphic.

Double clink on an (element) line, wire, rectangle generates highlighted line/wire section endpoints.

All (elements) lines,nodes,rectangles can be moved with one left-mouse depression.