Types of Differential Amplifiers
Differential Amplifiers: Topologies, Descriptions, Pros & Cons
This page discusses some of the most commonly used differential input / single-ended output amps in IC design. Each item includes a typical schematic, brief description, and advantages/disadvantages. Only CMOS amps are shown, but they can easily be converted to complementary BJT or complementary JFET. All discussion assumes the amps are used with negative feedback in small-signal applications.
If schematics are too large, use zoom (if you have it) to size the pics down.
Disclaimer: Steve is not a professor, and nothing on this page is peer-reviewed.
Originally, you could click the pic for more info. Sorry, this is now gone.
Contents
How to Read the Schematics
The well terminal connections are usually not indicated. This is to minimize visual clutter.
Except where noted, NFET wells can go to ground and PFET wells to VDD.
Often the body effect is preferably avoided, in which case the FETs' wells ideally tie to their sources when possible. This is sometimes shown in the schematics when the need seems greatest.
1X, 2X, etc., indicate relative W/L ratios.
I, 2I, etc., indicate relative current ratios.
A gain stage is sometimes included. The gain stage is not part of the diff amp, but is shown because it usually is included when the diff amp is used.
Compensation, when shown, is a kind typically, but not always used. Compensation is only needed in amplified networks with negative feedback.
Gate bias inputs must be generated by separates circuits not shown here. Usually, pBias and nBias respectively denote a PMOS or NMOS gate voltage intended to set a known current. nCas and pCas typically denote gate biases for cascode devices.
Nomenclature in this Article
gm = transconductance = ∂IDS / ∂VGS
gds = channel conductance = ∂IDS / ∂VDS = 1/rds
MIN (X, Y) = the lesser of X and Y
MAX (X, Y) = the greater of X and Y
Vcm = common mode input voltage = (PLUS + MINUS) / 2
VDS = drain to source voltage. Sometimes VDS is accidentally or sloppily used to mean -VDS, or VSD, for a PMOS.
VDsat = gate drive (|VGS| - |VT|) required for the designed-in current.
VDsatN = VDsat for an NMOS
VDsatP = the VDsat for a PMOS. This is not the minimum VDS, but the minimum VSD, to maintain saturation.
VG = gate voltage
VTn = NMOS threshold voltage
VTp = the negative of the PMOS threshold voltage. Usually a PMOS VT is negative, but it is convenient to think of it as positive. Thus on this webpage VTp denotes |VTp|.
A MOS transistor is only in its appropriate amplification mode if VDS >= VDsat (or for a PFET, VSD > VDsat). Thus, VDsat is the minimum VDS (or VSD) required for correct operation.
Technically, VDsat and the gate overdrive voltage are not the same. The distinction is usually minor but should be noted. VDsat is the minimum VDS (or VSD for PMOS) required for saturation. Gate overdrive voltage = VGS - VT (VSD + VTp for PMOS) and sets the current. For most practical purposes, VDsat - the gate overdrive. This author has chosen not to distinguish between the two.
As above, I often type portions of the text in bold for enhanced readability.
Amplifier Input & Output Limitations
Amplifier inputs and outputs are limited by the following factors:
Must not cause a transistor to exit saturation. The requirement for saturation is:
VGS - VTn >= VDS for NMOS
VSG - VTp >= VSD for PMOS
This assumes the convention that represents VTp as a positive number, even though technically it is (usually) negative.
Common-mode input must not cause the input pair's DC operating current to decrease from the designed value.
A decrease would alter the small-signal parameters. This occurs when VGS - VTn - VDsatN < VDS for an NMOS, or VSG - VTp - VDsatP
A decrease down to zero would kill the amp. This occurs when VGS - VTn <= 0 for an NMOS, or VSG - VTp <= 0 for a PMOS
The above factors are used to calculate the limitations on input and output voltages for the amplifiers shown. However, becasue the transition into triode is not abrupt, amplifier performance may degrade even when voltages are within but near the boundaries of these limitations.
Plain 5-Transistor Diff Amp
5T Amp: PMOS Inputs, Single-Ended Output
Inputs can go low
Output swing limited by input. A1OUT <= Vcm - VTp
Needs 2nd stage (shown) for wide swing
Description
Shown are the diff amp (left), a typical gain stage (right), and typical Miller compensation.
MP1 & MP2 form the "input pair." These are the transconductors.
MN1, MN2 form a current mirror, reflecting MP1's pullup current into a sink on MP2's drain.
A1OUT is the amplifier's output.
When PLUS rises, Vout rises. When MINUS rises, Vout falls.
PBIAS is reference gate voltage that mirrors a current from a reference cicruit that must be designed separately.
Diff amp gain (DC) = gm / [ gds(MN2) + gds(MP2) ], where gm = the transconductance of MP1 = the transconductance of MP2.
DC Gain of both stages combined = gm(MP2)*gm(MNout) / [gds(MN2) + gds(MP2)][gds(MPout) + gds(MNout) + any output load's conductance)
Distinguishing Features
Input voltages can go low but not high:
PLUS lower limit = VDsatN - VTp, since PLUS + VTp must be >= VDsatN for both FETs to be in saturation.
If A1OUT must swing very low, PLUS is further constrained, since to maintain saturation PLUS >= A1OUT - VTp.
MINUS lower limit = VDsatN - VTp, since MINUS + VTp must be >= VDsatN.
PLUS & MINUS upper limit = VDD - 2VDsatP - VTp, because:
MP0 is in triode unless its drain <= VDD - VDsatP
Input transistors MP1 & MP2 cannot conduct their designed current if unless their gate voltages are at least VTp + VDsatP less than their source.
Limited output (A1OUT) swing:
Min A1OUT = VDsatN
Max A1OUT = MIN [ MINUS + VTp, VDD - 2VDsatP ]
Swings beyond the above limits put transistors into triode.
2nd stage shown above fixes this limitation - 2nd stage output is full-swing.
Gain Stage
Because the 5T diff amp's output swing is limited, a gain stage like the one shown is usually added. Because of this gain stage, Vout can swing as high as VDD - VDsatP and as low as VDsatN. This is nearly always a wide enough output range.
For a PMOS-input diff amp:
The output should go to the NFET of the gain stage.
The gain stage's pulldown should be an NFET matched to the diff amp's NFETs.
The gain stage's pullup should be a current source matched to the diff amp's current source, such that the current density through the NFET matches that of the NFETs of the diff amp.
These rules cause all transistors' operating parameters to match each other when the amplifier's inputs are equal. Deviations from these rules will cause an input offset.
5T Amp: NMOS Inputs, Single-Ended Output
Inputs can go high.
Output swing limited by input. A1OUT >= Vcm - VTn.
Needs 2nd stage (shown) for wide swing
Description
Shown are the diff amp (left), a typical gain stage (right), and typical Miller compensation.
MN1 & MN2 form the "input pair." These are the transconductors.
MP1, MP2 form a current mirror, reflecting MN1's pulldown current into a source on MN2's drain.
A1OUT is the amplifier's output.
When PLUS rises, Vout rises. When MINUS rises, Vout falls.
NBIAS is reference gate voltage that mirrors a current from a reference cicruit that must be designed separately.
Diff amp gain = gm / [ gds(MN2>) + gds(MP2) ], where gm = the transconductance of MN1 = the transconductance of MN2.
Distinguishing Features
Input voltages can go high but not low:
PLUS, MINUS lower limit = 2VDsatN + VTn, since PLUS - VTn - VDsatN and MINUS - VTn - VDsatN must be >= CommonSource >= VDsatN
PLUS upper limit = MIN[ VDD - VDsatP + VTn + VDsatN, (minimum A1OUT) + VTn ].
In the case shown, with the gain stage used above, A1OUT probably needs to go as high as about VDD - VTp.
MINUS upper limit = VDD - VTp - VDsatP + VTn
Limited output (A1OUT) swing:
Min A1OUT = MAX [ PLUS - VTn, 2VDsatN ]
Max A1OUT = VDD - VDsatP
2nd stage shown above fixes this limitation.
Gain Stage
Because the 5T diff amp's output swing is limited, a gain stage like the one shown is usually added. Because of this gain stage, Vout can swing as high as VDD - VDsatP and as low as VDsatN. This is nearly always a wide enough output range.
For an NMOS-input diff amp:
The output, A1OUT, should go to the PFET of the gain stage.
The gain stage's pullup should be a PFET matched to the diff amp's PFETs.
The gain stage's pulldown should be a current source matched to the diff amp's current source, such that the current density through the PFET matches that of the PFETs of the diff amp.
These rules cause all transistors' operating parameters to match each other when the amplifier's inputs are equal. Deviations from these rules will cause an input offset.
Matching
Input pair MN1, MN2 is a critical match.
Current mirror MP1, MP2 is also a critical match, though in some cases slightly less so.
MPout should match the other PFETs, and MNout the other NFETs, but this matching is less important.
OTA (Operational Transconductance Amplifier)
Operational Transconductance Amp: Differential PMOS Inputs, Single-Ended Output
Inputs can go low
Full output swing, not limited by input.
Increased mismatch sensitivity (2 mirrors in series)
Description
Wide output swing using only one stage.
No additional stages needed unless more gain required.
The wide-swing output is the only high-impedance node - only one low-frequency pole.
Gain = gm / [ gds(MPout) + gds(MNout>) ] where gm = transconductance of MP1 = transconductance of MP2.
Max input common mode voltage (Vcm) = VDD - 2VDsatP - VTP
No minimum Vcm, but the designer should always avoid huge VGS values.
Miller compensation would be between VOUT and MINUS.
I believe the OTA is called:
Operational because its output is full-swing, limited only by the VDsat of the pullup and pulldown.
Transconductance because in small-signal analysis it feeds into its output impedance a current proportional to the differential input.
This transconductance gm(amp) = N * gm(MP1) = N * gm(MP2)
N = mirror ratio = (W/L)MPout / (W/L)MP3 = (W/L)MNout / (W/L)MN2 typically.
Amplifier, obviously, because it amplifies.
The 5T amplifier transconducts and amplifies, but I think does not count as operational, since it needs an added series stage for a full-swing output.
Matching
Diff pair MP1, MP2 is a critical match.
All 3common-gate current mirror pairs should be very well-matched. I.e., match MN2 to MNout, MN1 to MN3, &MP3 to MPout.
Mismatch in all four of the above pairs are error sources. These add up, so match these devices well.
Matching between one mirror pair and another pair is not critical.
MN1 to MN2 matching is not critical, because their characteristics have only 2nd-order effects.
Designers often consider current mirror matching to be non-critical. This only holds when:
the mirror transconductance << the input pair transconductance
there is only one mirror. In an OTA there are THREE mirrors. This multiplies their effective mismatch by a factor of 1.7.
Operational Transconductance Amp: Differential NMOS Inputs, Single-Ended Output
Inputs can go high
Full output swing, not limited by input.
Increased mismatch sensitivity (2 mirrors in series)
See the PMOS input OTA discussion. The difference of note is that the inputs can go high for an NMOS-input OTA and low for a PMOS-input OTA.
Folded Cascode OTA, NMOS Inputs
Advantages
High gain in one stage.
Relatively high input and output ranges.
Many variations of the folded cascode amplifier exist. Consult the External Links list.
The VCasN FET MN3 under the diff pair is often exluded.
For PMOS inputs, change N to P, P to N, and flip upside down.
Notice the 2X current in the upper PFETs. This doubles their gds (gds = ∂IDS / ∂VGS = λID ∝ ID), reducing the gain.
Folded Cascode OTA, PMOS Inputs
OTA with Cascode Current Mirrors
Higher Gain than Folded Cascode
Rather High Output Swing
Input Swing Similar to OTA & Folded Cascode
Can Use Smaller Miller Cap
Increased Mismatch Sensitivity (2 mirrors in series)
This is used in the author's 800mV voltage reference reported in the Designs page. This does not seem to be as common in the industry as the non-cascode version, except in cases when the cascodes serve as voltage protection. For instance, MPcas limits the VGS of MPout, and MNcas limits the VGS of MNout. But usually, this much gain is not needed in one stage.
Preferably tie all FETs' tanks to their sources, to increase headroom by removing body effect. Equations below assume this has been done.
Gain = gm(MP1) * [ gm(MPCas) * rds(MPcas) * rds(MPout) || gm(MNcas) * rds(MNcas) * rds(MNout) ]
Higher than folded cascode, since there is no divsion by 2 of PMOS rds.
Only 1 low-frequency pole.
Output Swing: 2VDsatN < Vout < VDD - 2VDsatP
Input Common Mode Range:
Vcm < VDD - 2VDsatP - VTp to avoid cutoff of input pair
Vcm > 2VDsatN - VTp to avoid triode condition in NMOS pulldowns
Lots of mirroring - increases sensitivity to mismatch.
Performance and complexity seem comparable to folded cascode
Can compensate with smaller Miller cap than for most amps with the same gain, because Rout is so high. Required Miller size depends on Gm but not Rout. So for the same gain can use a lower Gm and much smaller Miller cap. This advantage should only manifest when high DC gain is required, because this amp will very likely have high DC gain.
This OTA converts a differential input to a single-ended output. The input pair is not cascoded, because the gain loss from not cascoding ~ gds/gm ~ 0. It might be argued that MNCas1, MNCas3 and MNCas4 similarly offer negligible benefit, but if matching is good they will reduce input offset. A pure telescopic OTA is impractical for unity-gain configuration, but this circuit above does not have that restriction.
Telescopic Cascode Amp
High Gain, One Major Pole
Inappropriate for Unity-Gain Config
Folded Cascode More Flexible
Shown: Differential to Single-Ended with PMOS Inputs
Telescopic cascoding means the cascoding is in series. Compare to the folded cascode, which "folds" MP1 & MP2 downward into a pair of NMOS pulldowns.
Important Notes:
Fully differential and NMOS-input versions also exist.
PCas and NCas must be set carefully.
Unity-gain config is highly restrictive:
Vout = Minus = Plus
To keep MP4 saturated, we need Vout <= VTp + PCas
To keep MP2 out of triode, N1 <= Minus + VTp = Vout + VTp. Therefore Vout >= N1 - VTp.
Therefore VTp + PCas >= Vout >= N1 - VTp.
Since PCas = N1 - VSG4, VTp + N1 - VSG4 >= Vout >= N1 - VTp
Max possible output swing = 2VTp - VSG4
This analysis is discussed in C Yang's very helpful paper.
Folded cascode is much less limited and works well in unity-gain configuration.