Designs

IC Designs Page

* Schematics * Design Methods * Intensive Analysis * Simulation Results *

My Designs

Shown are design reviews for circuits I designed in my spare time as practice, using free tools.  These are completely separate from the many unpublished designs I have done for industry.  They're also starting to get kind of old, and certainly use only planar CMOS technology.

800mV CMOS Voltage Reference (Vref_Trim_buf.pdf) with:

• Bandgap Reference (P+ / N- / P-substrate PNP)

• Trimmable Resistor Divider

• Unity-Gain OTA with 72 dB power supply rejection (PSR) at 50 KHz, nominal conditions.

• 1.8V <= VDD <= 2.8V power supply spec

• PSR of complete circuit is 33 dB (nominal) at 50 KHz.  Small filter increases rejection to 41 dB.

• Uses < 11pF total cap

The circuit was designed with artificial, non-production models using LTspice for schematic capture and simulation.

Buck Converter - Top-Level Plan

• This design was begun some time ago, and simulated to a degree, but as my interests have changed, I might never finish this.  Any time spent toward this design might be better spent reviewing basic physics.

Another bandgap reference design appears as an example in the Control Theory PDF on my Tutorials page.

Appropriate use and distribution is free, but do not sell this material or claim copyrights for what I wrote.  These papers are not peer-reviewed and may contain occasional errors.

Others' Designs

The below designs are thorougly documented.  I used to have more links, but they tend to break faster than I can replace them.

High PSR Bandgap Ref for Ph.D Project

Uses a pumped gate NMOS in series with output PFET source, to reject supply ripple.  This paper, however, is not optimized for skimming.

Buck Regulator with Series LDO

The buck does not use a PWM (pulse-width modulator) but a hysteretic comparator that switches the converter between full-on and full-off modes.

See my design paper(s) below!