Shinya Takamaeda-Yamazaki, Ph.D.
Division of Electronics for Informatics,
Research Center of Mathematics for Social Creativity,
Research Institute for Electronic Science (Additional Post),
- Computer Architecture
- FPGA System
- High-level Synthesis
- Memory System
- Network on Chip
- Veriloggen: A library for constructing a Verilog HDL source code in Python
- PyCoRAM: Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
- Available at GitHub and PyPI.
- CARL2013 slide is here.
- The website of the original CoRAM memory architecture developed at CMU is here.
- Pyverilog: Python-based Hardware Design Processing Toolkit for Verilog HDL
- Tutorial of how to create a custom hardware on Xilinx Zynq with Debian Linux
- Available at Slideshare
- It can be applied to Altera DE1-SoC with OpenCL.
- E-mail: takamaeda_at_ist_hokudai_ac_jp
- Access to our laboratory
- Slideshare: my presentation and tutorial slides