Activity
Last Updated: April 1, 2022
Please see the publication list of our lab for the latest publications.
Publication
(Please see the Japanese page for the full publication list.)
Journal
Yafei Ou, Prasfoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, and Masayuki Ikebe: Real-time tone mapping: a survey and cross-implementation hardware benchmark, IEEE Transactions on Circuits and Systems for Video Technology, February 2021.
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, and Tadahiro Kuroda: A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.68, No.2, pp.692-703, Febuary 2021.
Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, and Masato Motomura: Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture, IEEE Access, Vol.9, pp.6179-6187, 2021.
Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, and Masato Motomura: STATICA: A 512-Spin 0.25M-Weight Annealing Processor with an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions, IEEE Journal of Solid-State Circuits, Vol.56, Issue.1, pp.165-178, October 2020.
Yuki Hirayama, Tetsuya Asai, Masato Motomura, and Shinya Takamaeda-Yamazaki: A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks, International Journal of Networking and Computing, Vol.10, No.2, pp.84-93, July 2020.
Prasoon Ambalathankandy, Masayuki Ikebe, Takashi Yoshida, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai: An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA, IEEE Transactions on Circuits and Systems for Video Technology, Vol.29, 2019.
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, and Shinya Takamaeda-Yamazaki: FPGA-based annealing processor with time-division multiplexing, IEICE Transactions on Information and Systems, Vol.E102-D, 2019.
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, and Masato Motomura: Dither NN: hardware/algorithm co-design for accurate quantized neural networks, IEICE Transactions on Information and Systems, Vol.E102-D, 2019.
Tatsuya Kaneko, Kentaro Orimo, Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: A Study on a Low Power Optimization Algorithm for an Edge-AI Device, IEICE Transactions on Nonlinear Theory and Its Applications, Vol.10, No.4, pp.373-389, October 2019.
Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, and Tetsuya Asai: Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks, Journal of Signal Processing, Vol.23, No.4, pp.151-154, July 2019.
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, and Masato Motomura: QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3D SRAM Using Inductive Coupling Technology in 40-nm CMOS, IEEE Journal of Solid-State Circuits, Vol.54, pp.186-196, January 2019.
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, and Shinya Takamaeda-Yamazaki: Quantization Error-Based Regularization for Hardware-Aware Neural Network Training, IEICE Transactions on Nonlinear Theory and Its Applications, Vol.9, No.4, pp.453-465, October 2018.
Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Masayuki Ikebe, Tetsuya Asai, and Hotaka Kusano: Real-Time HDTV to 4K and 8K-UHD Conversions using Anti-Aliasing based Super Resolution Algorithm on FPGA, Microprocessors and Microsystems, Vol.61, pp.21-31, September 2018.
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, and Masato Motomura: BRein Memory: A Single-chip Binary/Ternary Reconfigurable In-memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W, IEEE Journal of Solid-State Circuits, Vol. 12, pp.983-994, February 2018.
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, and Yasuhiko Nakashima: A Tree-based Checkpointing Architecture for the Dependability of FPGA Computing, IEICE Transactions on Information and Systems, Vol.E101-D, No.2, pp.288-302, February 2018.
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing, Complexity, Vol. 2018, pp.3618621-1-11, February 2018.
Takuto Tsuji, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: 6-DoF Camera Position and Posture Estimation based on Local Patches of Image Sequence, Journal of Signal Processing, Vol.21, 2017.
Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors, IEICE Transactions on Nonlinear Theory and Its Applications, Vol.8, No.3, pp.235-245, July 2017.
Kota Ando, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, and Masato Motomura: A Multithreaded CGRA for Convolutional Neural Network Processing, Circuits and Systems, Vol.8, No.6, pp.149-170, June 2017.
Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator, Circuits and Systems, Vol.8, No.5, pp.134-147, May 2017.
Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima: Performance Optimization of Light-field Applications on GPU, IEICE Transactions on Information and Systems, Vol.E99-D, No.12, pp.3072-3081, December 2016.
Shinya Takamaeda-Yamazaki, Hiroshi Nakatsuka, Yuichiro Tanaka, and Kenji Kise: Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs, IEICE Transactions on Information and Systems, Vol.E98-D, No.12, pp.2150-2158, December 2015.
Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, and Yasuhiko Nakashima: Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators, IEICE Transactions on Information and Systems, Vol.E98-D, No.12, pp.2141-2149, December 2015.
International Conference
Keisuke Kamahori and Shinya Takamaeda-Yamazaki: GBA: Guided Branch Approximation, The Fourth Young Architect Workshop (YArch 2022) (Co-located with ASPLOS 2022), March 2022.
Yoshiki Fujiwara and Shinya Takamaeda-Yamazaki: ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design, The 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2021), July 2021.
Nobuho Hashimoto and Shinya Takamaeda-Yamazaki: An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising, 31st International Conference on Field-Programmable Logic and Applications (FPL 2021), August 2021.
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda: A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes, 2020 IEEE International Symposium on Circuits and Systems (ISCAS 2020), Seville, Spain, pp.1-5, May 2020.
Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, and Shinya Takamaeda-Yamazaki: Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs, 16th International Symposium on Applied Reconfigurable Computing (ARC 2020), Universidad de Castilla-La Mancha, Toledo, Spain, April 2020.
Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, and Masato Motomura: STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions, 2020 International Solid-State Circuits Conference (ISSCC 2020), San Francisco, USA, February 2020.
Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, and Masayuki Ikebe: Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band, 2019 International Conference on Digital Image Computing: Techniques and Applications, University of Western Australia, Perth, Australia, December 2019.
Shinya Takamaeda-Yamazaki, Shinya Fujisawa, and Shuichi Fujisaki: NNgen: A Model-Specific Hardware Synthesis Compiler for Deep Neural Network (Demonstration), Thirty-third Conference on Neural Information Processing Systems (NeurIPS 2019),Vancouver Convention Center, December 10, 2019.
Yuki Hirayama, Tetsuya Asai, Masato Motomura, and Shinya Takamaeda-Yamazaki: A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators, The 7th International Symposium on Computing and Networking (CANDAR 2019), Nagasaki Civic Center, Nagasaki, Japan, November 2019
Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, and Shinya Takamaeda-Yamazaki: DeltaNet: Differential Binary Neural Network, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2019) (Poster), Cornell Tech, New York, USA, p.39, July 2019.
Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, and Tetsuya Asai: Hardware-oriented Algorithm and Architecture for Generative Adversarial Networks (NCSP’19 Student Paper Award), The 2019 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Hilton Waikiki Beach Hotel, Honolulu, USA, March 2019.
Shunya Suzuki, Seunggoo Rim, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices, The 2019 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Hilton Waikiki Beach Hotel, Honolulu, USA, March 2019.
Koyo Minamikawa, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, and Tetsuya Asai: FPGA-based FORCE Learning Accelerator towards Real-time Online Reservoir Computing, The 2019 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Hilton Waikiki Beach Hotel, Honolulu, USA, March 2019.
Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, and Tetsuya Asai: Ternarized Backpropagation: A Hardware-oriented Optimization Algorithm for Edge-oriented AI Devices, The 7th RIEC International Symposium on Brain Functions and Brain Computer, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan, February 22-23, 2019.
Seunggoo Rim, Shunya Suzuki, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: Approach to Reservoir Computing with Schmitt Trigger Oscillator-based Analog Neural Circuits (Best Paper Award), The 7th Japan-Korea Joint Workshop on Complex Communication Sciences, C5, Alpensia, Pyengonchang, Korea, January 2019.
Kota Ando, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, and Masato Motomura: Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware (Best Paper Award), The 2018 International Conference on Field-Programmable Technology (FPT'18), Tenbusu-Naha Hall, Naha, Japan, December 2018.
Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, and Masayuki Ikebe: Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions, IEEE International Conference on Visual Communications and Image Processing (VCIP 2018), Tempus Hotel Taichung , Taichung, Taiwan, December 2018.
Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, and Tetsuya Asai: A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing, Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour, Seaside House, Okinawa Institute of Science and Technology, Okinawa, Japan, October 2018.
Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, and Shinya Takamaeda-Yamazaki: Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators, IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), Vietnam National University, Hanoi, Vietnam, September 2018.
Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, and Tetsuya Asai: Sparse Disparity Estimation using Global Phase Only Correlation for Stereo Matching Acceleration, 2018 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP 2018) (Poster), Calgary Telus Convention Center, Alberta, Canada, April 2018.
Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, and Masato Motomura: Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform (IEEE CEDA All Japan Joint Chapter SASIMI Young Researcher Award), The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2018), Kunibiki Messe, Matsue, Japan, March 2018.
Naoto Iwamaru, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: A Novel Iris-Center Detection Algorithm Towards Gaze Estimation Targeting Molecular Cellular Automata, International Workshop on Molecular Architectonics 2018 (Poster), Osaka University, Osaka, Japan, March 2018.
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, and Masato Motomura: QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS (Silkroad Award), 2018 International Solid-State Circuits Conference (ISSCC 2018), San Francisco, February 2018.
Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, and Masato Motomura: Accelerating Deep Learning by Binarized Hardware, Asia-Pacific Signal and Information Processing Association Annual Summit and Conference 2017 (APSIPA ASC 2017), Aloft Kuala Lumpur Sentral Sentral, Kuala Lumpur, Malaysia, December 2017.
Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, and Shinya Takamaeda-Yamazaki: Quantization Error-based Regularization in Neural Networks, Thirty-seventh SGAI International Conference on Artificial Intelligence (SGAI 2017) (Poster), Peterhouse College, Cambridge, England, December 2017.
Itaru Hida, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: Sign-Invariant Unsupervised Learning Facilitates Weighted-Sum Computation in Analog Neural-Network Devices, 2017 International Symposium on Nonlinear Theory and Its Applications, Cancun International Convention Center, Cancun, Mexico, December 2017.
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, and Masato Motomura: Logarithmic Compression for Memory Footprint Reduction in Neural Network Training, 5th International Workshop on Computer Systems and Architectures (CSA 2017), Aomori Prefecture Tourist Center, Aomori, Japan, November 2017.
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, and Shinya Takamaeda-Yamazaki: A Regularization Approach for Quantized Neural Networks, International Workshop on Highly Efficient Neural Networks Design (HENND 2017) (Poster), Lotte Hotel City Center, Seoul, Korea, October 2017.
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: FPGA Implementation of Edge-Guided Pattern Generation for Motion-Vector Estimation of Textureless Objects, 27th International Conference on Field Programmable Logic and Applications (FPL 2017) (Demo Night), Culture and Convention Center Het Pand, Ghent, Belgium, September 2017.
Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Tadahiro Kuroda, and Masato Motomura: In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks, 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Tufts University, Boston, USA, August 2017.
Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, and Masato Motomura: Hardware Accelerator Design for Convolutional Neural Networks with Low Bit Precision, GI-CoRE GSQ, GSB, and IGM Joint Symposium -Quantum, Informatics, Biology, and Medicine, Hokkaido University, Japan, July 2017.
Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: A Versatile and Energy-Efficient Reconfigurable Accelerator for Embedded Microprocessors, GI-CoRE GSQ, GSB, and IGM Joint Symposium -Quantum, Informatics, Biology, and Medicine, Hokkaido University, Japan, July 2017.
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, and Shinya Takamaeda-Yamazaki: Time-Division Multiplexing Ising Machine on FPGAs, GI-CoRE GSQ, GSB, and IGM Joint Symposium -Quantum, Informatics, Biology, and Medicine, Hokkaido University, Japan, July 2017.
Kasho Yamamoto, Huang Weiqiang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, and Masato Motomura: A Time-Division Multiplexing Ising Machine on FPGAs, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2017), Ruhr University, Bochum, Germany, June 2017.
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, and Masato Motomura: BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator in 65 nm CMOS, 2017 Symposia on VLSI Technology and Circuits, Rihga Royal Hotel, Kyoto, Japan, June 2017.
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, and Yasuhiko Nakashima: CPRring: A Structure-aware Ring-based Checkpointing Architecture for FPGA Computing, The 25th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM2017) (Poster), April 2017.
Kasho Yamamoto, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, and Masato Motomura: A Scalable Ising Model Implementation on an FPGA, IEEE Symposium on Low-Power and High-Speed Chips 2017 (COOL Chips 20) (Poster), April 2017.
Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, and Tetsuya Asai: 6-DoF Camera-Position and Posture Estimation based on Local Patches of Image Sequence (NCSP’17 Student Paper Award), 2017 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2017), Hyatt Regency Guam, Guam, USA, February 2017.
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, and Masato Motomura: Throughput Analysis of a Data-flow Reconfigurable Array Architecture for Convolutional Neural Networks, The 5th RIEC International Symposium on Brain Functions and Brain Computer, Tohoku University, Sendai, Japan, February 2017.
Hoang Gia Vu, Supasit Kajkamhaeng, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima: CPRtree: A Tree-based Checkpointing Architecture for Heterogeneous FPGA Computing, 4th International Symposium on Computing and Networking (CANDAR 2016), November 2016.
Keisuke Fujimoto, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima: Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs, 4th International Workshop on Computer Systems and Architectures (CSA 2016), November 2016.
Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Tran Thi Hong, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima: CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis, 4th International Workshop on Computer Systems and Architectures (CSA 2016), November 2016.
Shohei Takeuchi, Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima: A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations, 3rd International Workshop on Computer Systems and Architectures (CSA’15), December 2015.
Thi Hong Tran, Hiromasa Kato, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima: Performance Evaluation of 802.11a Viterbi Decoder for IoT Applications, 8th International Conference on Advanced Technologies for Communications (ATC 2015), October 2015.
Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, and Yasuhiko Nakashima: A CGRA-based Approach for Accelerating Convolutional Neural Networks, IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-15), pp.73-80, September 2015. [slide]
Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer Science, Vol.9040/2015, pp.451-460, April 2015.
Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, and Yasuhiko Nakashima: A Parameterized Many Core Simulator for Design Space Exploration (Featured Poster Award), IEEE Symposium on Low-Power and High-Speed Chips 2015 (COOL Chips XVIII) (Poster), Yokohama Japan, April 2015.
Shinya Takamaeda-Yamazaki, and Kenji Kise: A Framework for Efficient Rapid Prototyping by Virtually Enlarging FPGA Resources, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2014), December 2014. [slide]
Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, and Yasuhiko Nakashima: Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators, International Workshop on Computer Systems and Architectures (CSA’14) (held in conjunction with CANDAR’14), December 2014.
Shinya Takamaeda-Yamazaki, and Kenji Kise: flipSyrup: Cycle-Accurate Hardware Simulation Framework on Abstract FPGA Platforms, 24th International Conference on Field Programmable Logic and Applications (FPL 2014) (Poster), September 2014.
Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, and Kenji Kise: Ultrasmall: The Smallest MIPS Soft Processor, 24th International Conference on Field Programmable Logic and Applications (FPL 2014) (Poster), September 2014.
Shinya Takamaeda-Yamazaki, Kenji Kise, and James C. Hoe: PyCoRAM: Yet Another Implementation of CoRAM Memory Architecture for Modern FPGA-based Computing, Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013) (Co-located with MICRO-46), December 2013. [slide]
Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, and Kenji Kise: Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations, Workshop on Challenges on Massively Parallel Processors (CMPP 2012) (in conjunction with ICNC’12), pp.343-349, December 2012.
Takakazu Ikeda, Shinya Takamaeda-Yamazaki, Naoki Fujieda, Shimpei Sato, and Kenji Kise: Read Density Aware Fair Memory Scheduling (Performance Track Award), 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3): Memory Scheduling Championship (MSC) (in conjunction with ISCA-39), June 2012.
Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, and Kenji Kise: ScalableCore System: A Scalable Many-core Simulator by Employing Over 100 FPGAs, 8th International Symposium on Applied Reconfigurable Computing (ARC 2012), Lecture Notes in Computer Science, Vol.7199/2012, pp.138-150, March 2012. [slide]
Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, and Kenji Kise: An FPGA-based Scalable Simulation Accelerator for Tile Architectures, ACM COMPUTER ARCHITECTURE NEWS, Vol.39, No.4, pp.38-43, September 2011 (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies HEART2011, pp.35-40, June 2011). [slide]
Shimpei Sato, Shinya Takamaeda, and Kenji Kise: DMR mode of SmartCore system, IEEE Pacific Rim International Symposium on Dependable Computing (PRDC’10) (Poster), National Institute of Informatics Japan, December 2010.
Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise: SmartCore System for Dependable Many-core Processor with Multifunction Routers, International Conference on Networking and Computing (ICNC’10), pp.133-139, November 2010. [slide]
Yuhta Wakasugi, Naoki Fujieda, Shinya Takamaeda, and Kenji Kise: MipsCoreDuo: A Multifunction Dual-core Processor, International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp.587-590, December 2009.
Shinya Takamaeda, Shimpei Watanabe, Takefumi Miyoshi, and Kenji Kise: ScalableCore: The Concept of Practical and Low-Cost Prototyping System for Many-Core Processor Research and Education, The 4th Workshop on Architectural Research Prototyping (WARP 2009) (in conjunction with ISCA 2009), Austin, June 2009.
Shinya Takamaeda, Shimpei Watanabe, Shimpei Sato, Koh Uehara, Yuhta Wakasugi, Naoki Fujieda, Yosuke Mori, and Kenji Kise: ScalableCore : High-Speed Prototyping System for Many-Core Processors, IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips 2009) (Poster), Yokohama Japan, p.161, April 2009.
Domestic Workshop
Keisuke Fujimoto, Takashi Nakada, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima: A Multi-Level Power-Capping Mechanism for FPGAs (Outstanding M2 Student Award (OM2)), The 1st. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2017), April 2017.
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima: A Framework for Tree-based Checkpointing Architecture on FPGAs, IPSJ Technical Report, SLDM2017-178, pp.1-6, January 2017.
Yuttakon Yuttakonkit, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima: Design Space Exploration of Computational Photography Accelerator, IEICE Technical Report CPSY2015-17, B-Con Plaza Beppu, pp.7-12, August 4, 2015.
Vu Hoang Gia, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima: A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications, IEICE Technical Report RECONF2015-15, Kyoto University, pp.79-84, June 20, 2015.
Oliver Kaltstein, Shinya Takamaeda-Yamazaki, Jun Yao and Yasuhiko Nakashima: DIVA-EMIN: Efficient Dependability for Post-Silicon Materials, IPSJ Kansai Section Convention 2014, Osaka University, September 2014.
Ryohei Kobayashi, Shinya Takamaeda-Yamazaki and Kenji Kise: Design of Synchronization Mechanism to Conquer the Clock Oscillator Variation for High Performance Stencil Computation Accelerator, The 75th IPSJ National Convention, Tohoku University, March 2013.
Shinya Takamaeda-Yamazaki, Naoki Fujieda and Kenji Kise: Network Performance of Multifunction On-chip Router Architectures, IEICE Technical Report CPSY2012-52, Kyushu University, November 2012. [slide]
Oral Presentation
Shinya Takamaeda-Yamazaki: Invited Talk (Mini Keynote), Model/Architecture Co-design for Accurate Binary Neural Network, 19th International Forum on MPSoC for Software-defined Hardware (MPSoC 2019), The Prince Hakone Lake Ashinoko / Hakone, Kanagawa, Japan, July 2019.
Shinya Takamaeda-Yamazaki: Invited Talk, Architecture/Algorithm Co-design for Highly-Efficient Machine Learning Processing, Embedded Machine Learning Workshop (EML2018) (co-located with FPT'18), Tenbusu-Naha Hall, Naha, Japan, December 2018.
Shinya Takamaeda-Yamazaki: Invited Talk (Mini Keynote), QUEST: A Log-Quantized Deep Neural Network Engine with 3D Stacking SRAMs, 18th International Forum on MPSoC for Software-defined Hardware (MPSoC 2018), The Cliff Lodge/ Snowbird, UT, USA, July 2018.
Shinya Takamaeda-Yamazaki: Invited Talk (Keynote), Making Efficient Quantized Neural Network Engine by Hardware/Algorithm Co-Design, 27th International Workshop on Post-Binary ULSI Systems (ULSI 2018), Johannes Kepler University of Linz, Linz, Austria, May 2018.
Shinya Takamaeda-Yamazaki: Invited Talk (Keynote), Accelerating Deep Learning by Hardware/Algorithm Co-Design, International Workshop on Advances in Networking and Computing (WANC 2017), Aomori, Japan, November 2017.
Shinya Takamaeda-Yamazaki: Invited Talk (Mini Keynote), Energy-Efficient In-Memory Neural Network Processor, 17th International Forum on MPSoC for Software-defined Hardware (MPSoC 2017), Les Tresoms Hotel, Annecy, France, July, 2017.
Shinya Takamaeda-Yamazaki: Invited Talk (Mini Keynote), Customizable Hardware Abstraction, 16th International Forum on MPSoC for Software-defined Hardware (MPSoC 2016), Nara, Japan, July 2016.
Shinya Takamaeda-Yamazaki: A High Performance Heterogeneous FPGA-based Accelerator with PyCoRAM (Runner Up Award), Digilent Design Contest 2014 Japan Region, Yokohama, Japan, February 2014. [slide]
Dissertation
Doctor Thesis: Multi-FPGA based Prototyping Framework for Emerging Manycores (IPSJ Nominated Doctor Thesis (SIG ARC)), Graduate School of Information Science and Engineering, Tokyo Institute of Technology, February 2014.
Award
Seunggoo Rim, Shunya Suzuki, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, and Tetsuya Asai: Best Paper Award, Approach to Reservoir Computing with Schmitt Trigger Oscillator-based Analog Neural Circuits, The 7th Japan-Korea Joint Workshop on Complex Communication Sciences, C5, Alpensia, Pyengonchang, Korea, January 2019.
Kota Ando, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, and Masato Motomura: Best Paper Award, Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware, The 2018 International Conference on Field-Programmable Technology (FPT'18), December 2018.
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, and Masato Motomura: ISSCC 2018 Silkroad Award, QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS, 2018 International Solid-State Circuits Conference (ISSCC 2018), February 2018.
Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima: Featured Poster Award, A Parameterized Many Core Simulator for Design Space Exploration, IEEE Symposium on Low-Power and High-Speed Chips 2015 (COOL Chips XVIII) (Poster), Yokohama Japan, April 2015.
Shinya Takamaeda-Yamazaki: IPSJ Nominated Doctor Thesis (SIG ARC), Multi-FPGA based Prototyping Framework for Emerging Manycores, August 2014.
Shinya Takamaeda-Yamazaki: Runner Up, A High Performance Heterogeneous FPGA-based Accelerator with PyCoRAM, Digilent Design Contest 2014 Japan Region, February 2014.
Takakazu Ikeda, Shinya Takamaeda-Yamazaki, Naoki Fujieda, Shimpei Sato and Kenji Kise: Performance Track Award, Read Density Aware Fair Memory Scheduling, 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3): Memory Scheduling Championship (MSC) (in conjunction with ISCA-39), June 2012.
Award of My Students
Tatsuya Kaneko: NCSP’19 Student Paper Award, Hardware-oriented Algorithm and Architecture for Generative Adversarial Networks, The 2019 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Hilton Waikiki Beach Hotel, Honolulu, USA, March 2019.
Seunggoo Rim: Best Paper Award, Approach to Reservoir Computing with Schmitt Trigger Oscillator-based Analog Neural Circuits, The 7th Japan-Korea Joint Workshop on Complex Communication Sciences, C5, Alpensia, Pyengonchang, Korea, January 2019.
Kota Ando: Best Paper Award, Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware, The 2018 International Conference on Field-Programmable Technology (FPT'18), December 2018.
Kodai Ueyoshi: IEEE SSCS Predoctoral Achievement Award, QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS, December 1, 2018.
Ryota Uematsu: IEEE CEDA All Japan Joint Chapter SASIMI Young Researcher Award, Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform, The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2018) (Poster), Kunibiki Messe, Matsue, Japan, March 2018.
Kodai Ueyoshi: ISSCC 2018 Silkroad Award, QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS, 2018 International Solid-State Circuits Conference (ISSCC 2018), February 2018.
Keisuke Fujimoto: Outstanding M2 Student Award (OM2), A Multi-Level Power-Capping Mechanism for FPGAs, The 1st. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2017), April 2017.
Takuto Tsuji: NCSP'17 Student Paper Award, 6-DoF Camera-Position and Posture Estimation based on Local Patches of Image Sequence, 2017 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2017), Hyatt Regency Guam, Guam, USA, February 2017.
Shohei Takeuchi: Featured Poster Award, A Parameterized Many Core Simulator for Design Space Exploration, IEEE Symposium on Low-Power and High-Speed Chips 2015 (COOL Chips XVIII) (Poster), Yokohama Japan, April 2015.
Society Activity
International
IEEE International Conference on High Performance Computing (HiPC), Program Committee Member, 2021--
IEEE International Conference on Computers, Software & Applications (COMPSAC), Program Committee Member, 2018, 2020--
Asia and South Pacific Design Automation Conference (ASP-DAC), Technical Program Committee Member, 2020--
Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Technical Program Committee Member, 2018 (Design Experiences), 2019, 2021, 2022 (System Level Design)
IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Program Committee Member, 2018--
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips), Program Committee Member, 2017--
International Symposium on Computing and Networking (CANDAR), Program Vice-Chair (Track-2 Chair), 2017--
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Technical Program Co-Chairs, 2019
The International Conference on Field-Programmable Technology (FPT), Web Chair, 2018
IEEE/ACM International Symposium on Microarchitecture (MICRO), Registration Co-Chairs, 2018
International Forum on MPSoC for Software-defined Hardware, Organizing Committee Member, 2017--2018
ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Technical Program Committee Member, 2020
International Workshop on Machine Learning Systems Engineering (iMLSE), Technical Program Committee Member, 2020
ACM International Conference on Computing Frontiers (CF), Technical Program Committee Member, 2020
IEEE International Conference on Computer Design (ICCD), Technical Program Committee Member, 2019--2020
International Workshop on Advances in Networking and Computing (WANC), Program Committee Member, 2015--2020
The International Conference on Field-Programmable Technology (FPT), Program Committee Member, 2014, 2018--2019
International Conference on Parallel Processing (ICPP), Technical Program Committee Member, 2019
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Program Committee Member, 2017--2018
International Workshop on Computer Systems and Architectures (CSA), Program Committee Member, 2015--2017
International Symposium on Computing and Networking (CANDAR), Program Committee Member, 2014--2016
IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Local Arrangement Chair, 2016
International Forum on MPSoC for Software-defined Hardware, Proceedings Chair, 2016
Domestic
Cross-disciplinary workshop on computing Systems, Infrastructures, and programminG (xSIG), Program Vice-chairs, 2022
JSSST SIG-MLSE WG for Fundamentals of Systems, Secretary, FY 2019--
Cross-disciplinary workshop on computing Systems, Infrastructures, and programminG (xSIG), Program Committee Member, 2017--2021
IPSJ Transactions on Advanced Computing Systems (ACS), Editorial Committee Member, 2017--2020
IEICE Transactions on Information and Systems, Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking, Editor in chief, FY 2020
IEICE Transactions on Information and Systems, Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking, Guest Editor, FY 2019
IEICE Transactions on Information and Systems, Special Section on Parallel and Distributed Computing and Networking, Guest Editor, FY 2018
IEICE Working Group for Young Researchers, Member, FY 2020--2021
IPSJ SIG-ARC, Committee Member, FY 2018--2021
IEICE SIG-RECONF, Committee Member, FY 2016--2021
IEICE SIG-CPSY, Secretary, FY 2017--2020
IEICE SIG-CPSY, Assistant Secretary, FY 2015--2016
JACORN 2015, General Chair, 2015
IEICE SIG-ICD, Student Committee Member, FY 2011-2012
Research Grant
(Excluding collaboration research fundings)
JST CREST (Core technologies for trusted quality AI systems), PI, D3-AI: Distributed AI for Dynamic and Diverse Environments, FY 2021--2026
JSPS KAKENHI Grant-in-Aid for Scientific Research (B), PI, FY 2019--2022
NEDO (AI and Edge Computing), Collaborator (PI: Fixstars Corp.), FY 2018--2021
JST PRESTO (Innovative Computing), PI, Highly Efficient Deep Learning System by Architecture/Algorithm Co-Design, FY 2018--2021
JST CREST (Society 5.0), Collaborator (PI: Masato Motomura), Steering Toward Spatio-Temporal Computing Architecture Driven by Learning/Math-Scientific Models, FY 2018--2023
JSPS KAKENHI Grant-in-Aid for Scientific Research (S), Collaborator (PI: Masato Motomura), FY 2018--2022
NEDO (AI and Edge Computing), Collaborator (PI: Socionext Inc.), FY 2018--2020
JSPS KAKENHI Grant-in-Aid for Scientific Research (B), Collaborator (PI: Masayuki Ikebe), Bidirectional Conversion of Computation Capabilities between Deep Neural Network and Effective Image Processing, FY 2018--2020
Hokkaido University Step-up Support Grant, PI, 1,000,000 JPY, FY 2018
The 2nd Technova Prize, PI, Development of Efficient Deep Learning Accelerator via Numerical Representatin Optimization for IoT, 1,000,000 JPY, FY 2017
Hokkaido University Start-up Support Grant, PI, 1,000,000 JPY, FY 2016
JSPS KAKENHI Grant-in-Aid for Young Scientists (B), PI, A Framework for FPGA Accelerator Design with Maximum Memory Performance, 3,900,000 JPY (Direct 3,000,000 JPY, Indirect 900,000 JPY), FY 2016-2017
The Mazda Foundation, PI, Multi-paradigm Development Framework to Improve Programmability and Performance of FPGA Accelerators, 1,200,000 JPY, FY 2014-2016
JSPS Research Fellow, PI, Development of HW Simulators for Accelerating HW/SW Researches, 1,900,000 JPY, FY 2011-2013
Lecture
Advanced Custom Computing, Graduate School of Information Science and Technology, The University of Tokyo, FY 2020--
Computing Architecture, Department of Information Science, School of Science, The University of Tokyo, FY 2020--
Processor and Compiler Lab, Department of Information Science, School of Science, The University of Tokyo, FY 2020--
Computer Architecture and Design, Department of Information Science, School of Science, The University of Tokyo, FY 2020--
Hardware Architecture and Design, Department of Information Science, School of Science, The University of Tokyo, FY 2020--
Integrated Information Processing, Division of Electronics for Informatics, Graduate School of Information Science and Technology, Hokkaido University, FY 2017--2019
Introduction to Informatics I, Hokkaido University, FY 2017--2019
Digital Circuit Design, Department of Electronics and Information Engineering, School of Engineering, Hokkaido University, FY 2016--2018
Electrical and Electronic Engineering Laboratories, Department of Electronics and Information Engineering, School of Engineering, Hokkaido University, FY 2016--2018
System Application of LSIs, Division of Electronics for Informatics, Graduate School of Information Science and Technology, Hokkaido University, FY 2016
Reconfigurable Computing (lectured in English), Graduate School of Information Science, Nara Institute of Science and Technology, FY 2015--2016
Advanced Computing Architecture 1, Graduate School of Information Science, Nara Institute of Science and Technology, FY 2014--2016
Advanced Computing Architecture 2, Graduate School of Information Science, Nara Institute of Science and Technology, FY 2014--2016
Advanced Computing Architecture 3, Graduate School of Information Science, Nara Institute of Science and Technology, FY 2014--2016
Advanced Computing Architecture 4, Graduate School of Information Science, Nara Institute of Science and Technology, FY 2014--2016
Hardware Design 1 (lectured in English), Graduate School of Information Science, Nara Institute of Science and Technology, FY 2014
Biography
Work Experience
October 2019 - Present, Associate Professor, Department of Computer Science, Graduate School of Information Science and Technology, The University of Tokyo, Japan
October 2018 - March 2022, JST PRESTO Researcher (Concurrent Post)
April 2019 - September 2019, Associate Professor, Division of Electronics for Informatics, Graduate School of Information Science and Technology, Hokkaido University, Japan
December 2016 - September 2019, Associate Professor, Research Center of Mathematics for Social Creativity, Research Institute for Electronic Science, Hokkaido University, Japan
October 2016 - March 2019, Associate Professor, Department of Electronics for Informatics, Graduate School of Information Science and Technology, Hokkaido University, Japan
April 2014 - September 2016, Assistant Professor, Graduate School of Information Science, Nara Institute of Science and Technology, Japan
April 2011 - March 2014, JSPS Research Fellow (DC1)
June 2013 - July 2013, Visiting Scholar, Electrical and Computer Engineering, Carnegie Mellon University, US
June 2011 - August 2011, Internship, Fujitsu Laboratories, Japan
Education
2014 Received D.E. from Tokyo Institute of Technology, Japan
2011 Received M.E. from Tokyo Institute of Technology, Japan
2009 Received B.E. from Tokyo Institute of Technology, Japan
2007 Received Assoc. B.E. from Fukushima National College of Technology, Japan