Publication

Please see the Japanese page for domestic publications.

2025

Journal

• Tatsuya Kubo, Daichi Tokuda, Lei Qu, Ting Cao, and Shinya Takamaeda-Yamazaki, "PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM", IEEE Computer Architecture Letters, June 2025, Accepted.

International Conference

• Kotaro Shimamura, Ayumi Ohno, and Shinya Takamaeda-Yamazaki, "Exploring the Versal AI Engine for 3D Gaussian Splatting", IEEE Symposium on Low-Power and High-Speed Chips and Systems 2025 (COOL Chips 28), April 2025.

• Mebuki Oishi, Sun Tanaka, and Shinya Takamaeda-Yamazaki, "RustSFQ: A Domain-Specific Language for SFQ Circuit Design", IEEE Symposium on Low-Power and High-Speed Chips and Systems 2025 (COOL Chips 28), April 2025.

• Ayumi Ohno, Kotaro Shimamura, and Shinya Takamaeda-Yamazaki, "Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-scalar Multiplication", IEEE Symposium on Low-Power and High-Speed Chips and Systems 2025 (COOL Chips 28), April 2025.

• Shinya Takamaeda-Yamazaki, Invited Talk,"Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL", Special Session: 20 years of ARC: A Selection of Most Representative Papers, The 21st International Symposium on Applied Reconfigurable Computing (ARC 2025), April 2025.

• Mebuki Oishi, Sun Tanaka, and Shinya Takamaeda-Yamazaki, "Rust-Based Domain-Specific Language for SFQ Circuit Design", 5th Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE 2025), March 2025.

• Izumi Tanaka, Ken Sakayori, Shinya Takamaeda-Yamazaki, and Naoki Kobayashi, "High-Level Synthesis with Linear Types", 5th Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE 2025), March 2025.

Preprint

• Honoka Anada, Tatsuya Kaneko, and Shinya Takamaeda-Yamazaki, "How to Evaluate Participant Contributions in Decentralized Federated Learning", arXiv:2505.23246, May 2025.

• Tatsuya Kubo, Daichi Tokuda, Tomoya Nagatani, Masayuki Usui, Lei Qu, Ting Cao, and Shinya Takamaeda-Yamazaki, "MVDRAM: Enabling GeMV Execution in Unmodified DRAM for Low-Bit LLM Acceleration", arXiv:2503.23817, March 2025.

Article

• Shinya Takamaeda-Yamazaki, "Uncertainty in Machine Learning and Future Computers", IEEE Computer, Volume: 58, Issue: 4, pp.152-156, April 2025.

Presentation

• Yoshiki Ozaki and Shinya Takamaeda-Yamazaki, "Design and Implementation of Secure Memory Systems with XLS High-Level Synthesis", IEEE Symposium on Low-Power and High-Speed Chips and Systems 2025 (COOL Chips 28) (Poster), April 2025.

Master Thesis (Department of Computer Science)

• Masayuki Usui, "Adaptive Speculative Decoding for Low-Latency LLM Serving", January 2025.

• Kotaro Shimamura, "Exploring the Versal AI Engine for 3D Gaussian Splatting", January 2025.

• Sun Tanaka, "Efficient Single-Flux-Quantum Circuit Architecture for Deterministic Arithmetic with Delay Coding", January 2025.

Senior Thesis (Department of Information Science)

• Mebuki Oishi, "A Domain-Specific Language for SFQ Circuit Design Ensuring Input–Output Consistency", January 2025.

• Ayumi Ohno, "Exploring the Versal AI Engines for Multi-scalar Multiplication Acceleration", January 2025.

2024

Journal

• Daichi Tokuda and Shinya Takamaeda-Yamazaki, "DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination", ACM Transactions on Reconfigurable Technology and Systems, Vol.18, Issue.2, pp.1-26, March 2025.

• Honoka Anada, Ryu Sefutsu, Masayuki Usui, Tatsuya Kaneko, and Shinya Takamaeda-Yamazaki, "PRIOT: Pruning-Based Integer-Only Transfer Learning for Embedded Systems", IEEE Embedded Systems Letters, Vol.17, Issue.2, pp.87-90, April 2025.

• Yuki Hirayama and Shinya Takamaeda-Yamazaki, "Scalable Moment Propagation and Analysis of Variational Distributions for Practical Bayesian Deep Learning", IEEE Transactions on Neural Networks and Learning Systems, Vol.36, Issue.3, pp.4614-4624, March 2025.

• Tatsuya Kubo and Shinya Takamaeda-Yamazaki, "Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Non-Volatile Memory Systems", IEEE Micro, Vol. 44, No. 1, pp.38-48, January 2024.

International Conference

• Tatsuya Kubo, Masayuki Usui, Tomoya Nagatani, Daichi Tokuda, Lei Qu, Ting Cao, and Shinya Takamaeda-Yamazaki, "Bulk Bitwise Accumulation in Commercial DRAM", NeurIPS 2024 Workshop Machine Learning with new Compute Paradigms (MLNCP 2024), December 2024.

• Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Shinya Takamaeda-Yamazaki, and Kentaro Yoshioka, "PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation", 2024 ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2024), October 2024.

• Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, and Kentaro Yoshioka, "OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration", 29th Asia and South Pacific Design Automation Conference (ASP-DAC 2024), January 2024.

• Kotaro Shimamura, and Shinya Takamaeda-Yamazaki, "FS-Boost: Communication-Efficient Federated Subtree-based Gradient Boosting Decision Trees", IEEE Consumer Communications and Networking Conference 2024 (CCNC 2024), January 2024.

Preprint

• Shogo Nakakita, Tatsuya Kaneko, Shinya Takamaeda-Yamazaki, and Masaaki Imaizumi, "Federated Learning with Relative Fairness", arXiv:2411.01161, November 2024.

Doctoral Thesis (Department of Computer Science)

• Yuki Hirayama, "Bayesian Deep Learning with Computationally Efficient Uncertainty Quantification", January 2024.

Master Thesis (Department of Computer Science)

• Kohei Asano, "Finding Missing Automatic Vectorization Opportunity by Differential Testing", January 2024.

• Akira Iga, "Accelerating Function-Level Verification of Stream-Based High-Level Synthesis Compilers", January 2024.

• Tatsuya Kubo, "Neural Network Calibration for Efficient and Robust Analog Compute-in-Memory based on Large-Scale SRAM Arrays", January 2024.

• Kengo Suga, "Enhancing Efficiency in Bayesian Neural Network Inference through Dropout Pattern Optimization", January 2024.

• Masayoshi Tsutsui, "Poison Egg: Scrambling Federated Learning with Delayed Backdoor Attack", January 2024.

• Sefutsu Ryu, "Integer Transfer Learning via On-device Pruning", January 2024.

Senior Thesis (Department of Information Science)

• Honoka Anada, "Hardware-Efficient Transfer Learning via Lightweight Edge-Popup Algorithm", January 2024.

• Yoshiki Ozaki, "Configurable Neural Network Accelerator via Fine-Grained Computation Masking on Fixed Adder Trees", January 2024.

• Daichi Tokuda, "High-Performance Decision Forest Accelerator via Bit-Level Early-Termination", January 2024.

• Tomoya Nagatani, "Hardware High-Level Synthesis with Memory Integrity Verification", January 2024.

2023

Journal

• Peiqi Zhang and Shinya Takamaeda-Yamazaki, "MITA: Multi-Input Adaptive Activation Function for Accurate Binary Neural Network Hardware", IEICE Transactions on Information and Systems, Vol. E106-D, No. 12,  December 2023.

International Conference

• Sun Tanaka and Shinya Takamaeda-Yamazaki, "MAO: Memory Architecture Obfuscation", 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2023), December 2023.

• Yuki Hirayama, Kengo Suga, and Shinya Takamaeda-Yamazaki, "GeMP-BNN: High-Performance Sampling-Free Bayesian Neural Network Accelerator with Gaussian Error Moment Propagation", 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2023), December 2023.

• Masayoshi Tsutsui, Tatsuya Kaneko, and Shinya Takamaeda-Yamazaki, "Poison Egg: Scrambling Federated Learning with Delayed Backdoor Attack", 3rd International Conference on Ubiquitous Security 2023 (UbiSec-2023), November 2023.

• Masayuki Usui and Shinya Takamaeda-Yamazaki, "High-Level Synthesis of Memory Systems for Decoupled Data Orchestration", 19th International Symposium on Applied Reconfigurable Computing (ARC 2023), Semtember 2023.

• Tatsuya Kubo and Shinya Takamaeda-Yamazaki, "Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory", IEEE Symposium on Low-Power and High-Speed Chips and Systems 2023 (COOL Chips 26), April 2023.

• Masayoshi Tsutsui and Shinya Takamaeda-Yamazaki: SPinS-FL: Communication-Efficient Federated Subnetwork Learning, IEEE Consumer Communications and Networking Conference 2023 (CCNC 2024), January 2023.

Master Thesis (Department of Computer Science)

• Daichi Murakami, "Atomic Execution of Instruction Sequences using Local Register File to Reduce the Power Consumption of SIMT Processors", August 2023.

• Yinghao Ren, "Development of Dataflow-Oriented High-level Synthesis Compiler with Parameterized Parallel Abstraction", August 2023.

• Kota Kuga, "FPGA-Oriented Multiplication-Free CNN Accelerator", January 2023.

• Ryo Koike, "High-Performance and Low-Overhead Secure Non-Volatile Memory System", January 2023.

• Nobuho Hashimoto, "Acceleration of Video Depth Estimation for Embedded Devices", January 2023.

• Yoshiki Fujiwara, "Bit Pass: Dynamic Computation Balancing for Bit Sparsity Deep Learning Accelerator", January 2023.

Senior Thesis (Department of Information Science)

• Masayuki Usui, "Automatic Synthesis of Decoupled Data Orchestration Mechanisms from High-Level Hardware Descriptions", January 2023.

• Keisuke Kamahori, "Encrypted and Integrity-Protected Cache against On-Chip Threats", January 2023.

• Kotaro Shimamura, "Communication-Efficient Federated Learning Method for Gradient Boosting Decision Trees", January 2023.

• Sun Tanaka, "RTL Obfuscation of On-chip Memory Structures" (オンチップメモリ構造の RTL 難読化), January 2023.

• Tasuku Fukami, "Reducing Conflict Misses in Superblock-based Compressed Cache", January 2023.

Award

• Ryo Koike, IEEE CEDA AJJC Academic Research Award, November 2023.

• Shinya Takamaeda, The Young Scientists’ Award, The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology, FY 2023, "Research on Efficient AI by Hardware/Algorithm Co-design", April 2023.

2022

International Conference

• Nobuho Hashimoto and Shinya Takamaeda-Yamazaki, "FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design", International Conference on Field Programmable Technology (FPT 2022), December 2022.

• Sefutsu Ryu and Shinya Takamaeda-Yamazaki, "Model-based Federated Reinforcement Distillation", IEEE Global Communications Conference 2022 (GLOBECOM 2022), December 2022.

• Shinya Takamaeda-Yamazaki, Invited Talk "Algorithm/Hardware Co-design for Reliable AI", The 2022 International Meeting for  Future of Electron Devices, Kansai (IMFEDK 2022), November 2022.

• Peiqi Zhang and Shinya Takamaeda-Yamazaki, "Multi-Input Adaptive Activation Function for Binary Neural Networks" (CSA Best Paper Award), 10th International Workshop on Computer Systems and Architectures (CSA 2022), November 2022.

• Keisuke Kamahori and Shinya Takamaeda-Yamazaki, "Accelerating Decision Tree Ensemble with Guided Branch Approximation", International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies 2022 (HEART 2022), June 2022.

• Keisuke Kamahori and Shinya Takamaeda-Yamazaki, "GBA: Guided Branch Approximation", The Fourth Young Architect Workshop (YArch 2022) (Co-located with ASPLOS 2022), March 2022.

Preprint

• Yuki Hirayama, Sinya Takamaeda-Yamazaki, "MP-GELU Bayesian Neural Networks: Moment Propagation by GELU Nonlinearity",  arXiv:2211.13402, November 2022.

Senior Thesis (Department of Information Science)

• Tatsuya Kubo, "CacheSetHash: Efficient Integrity Verification Scheme for Secure Non-Volatile Memory", January 2022.

• Kengo Suga, "RAMSH: High-Performance Random-Access-Aware Memory System on High Bandwidth Memory", January 2022.

• Masayoshi Tsutsui, "SPinS-FL : Communication-Efficient Federated Hidden Neural Network with Selectively-Pinned Supermasks", January 2022.

• Sefutsu Ryu, "Model-based Federated Reinforcement Distillation", January 2022.

Award

• Peiqi Zhang and Shinya Takamaeda-Yamazaki: CSA Best Paper Award, Multi-Input Adaptive Activation Function for Binary Neural Networks, 10th International Workshop on Computer Systems and Architectures (CSA 2022), November 21, 2022.

2021

Journal

• Yafei Ou, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, and Masayuki Ikebe, "Real-time tone mapping: a survey and cross-implementation hardware benchmark", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 32, No. 5, pp.2666-2686, February 2021.

• Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, and Tadahiro Kuroda, "A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.68, No.2, pp.692-703, February 2021.

• Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, and Masato Motomura, "Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture", IEEE Access, Vol.9, pp.6179-6187, 2021.

International Conference

• Yoshiki Fujiwara and Shinya Takamaeda-Yamazaki, "ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design", The 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2021), July 2021.

• Nobuho Hashimoto and Shinya Takamaeda-Yamazaki, "An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising", 31st International Conference on Field-Programmable Logic and Applications (FPL 2021), August 2021.

Senior Thesis (Department of Information Science)

• Ryo Koike, "Odin: Efficient Crash-Consistency Support for Secure Non-Volatile Memory Using Hardware Logging", January 2021.

• Nobuho Hashimoto, "FPGA-Based Real-Time Image Denoising Accelerator Using Bilateral Grid with a Variable-Sized Window", January 2021.

• Yoshiki Fujiwara, "ASBNN: Acceleration of Variational Inference in Bayesian Convolutional Neural Networks by Algorithm/Hardware", January 2021.

Publications earlier than 2020, please refer to Takamaeda's page.