Resarch

Research Area

• Computer Architecture

• Processor Architecture and Memory System

• Hardware Security and Secure Processor

• Hardware Design Technology and High-Level Synthesis Compiler

• Algorithm/Hardware Co-design

• Machine Learning System, Distributed Machine Learning, and Federated Learning

• FPGA System

We are pursuing various research on highly efficient next-generation computers, such as custom computing employing FPGA and domain-specific hardware, algorithm/hardware co-design for machine learning, and high-level synthesis compilers for a productive hardware design environment. We are also pursuing software research on compilers, programming models, and frameworks for user/programmer-friendly computers.

Recent Research Projects

Federated Learning for Dynamic and Diverse Environments

• Communication-Efficient Federated Learning

• Security of Federated Learning (Backdoor Attack and Protection)

• Personalized Federated Learning

• Large-Scale Federated Learning Simulator and Platform

• Decision Tree Ensemble based Federated Learning

• Online Learning Algorithm/Accelerator

Domain-Specific Architecture and Machine Learning Accelerator

• DNN Training/Inference Accelerator (AI Chip)

• Hardware-Oriented DNN Algorithm (Quantized Neural Network, Binary Neural Network)

• Computation-Efficient Bayes Deep Learning Algorithm and Hardware

• Model Compression Algorithm for Hard-wired DNN Accelerators

• Hardware/Algorithm Co-design for Decision Tree Ensemble

• Accelerator for Multimodal AI and Robotics

Computer Architecture

• Secure Processor (Trusted Execution Environment; TEE)

• Memory Encryption and Integrity Verification

• Processing in Memory Circuit, Processor, and Compiler

• Energy-Efficient GPU Architecture

• Approximate Computing Architecture based on Stochastic Thermodynamics

Hardware Design Technology and Compiler

• Hardware Design Language and High-Level Synthesis Compiler

• Python-based Hardware Design Framework Veriloggen

• DNN Accelerator Synthesis Compiler NNgen 

• Hardware Description Obfuscation for IP Protection

• Covert Channel in Hardware Systems