Resarch

Research Topics

• Computer Architecture

  • Processor Architecture, Memory System

  • Domain-Specific Architecture, FPGA system

  • Secure Processor (TEE)

  • Compute-in-Memory

  • Computing with Emerging Devices

• Hardware Design Technology

  • High-Level Synthesis Compiler

  • Algorithm/Hardware Co-design

• Machine Learning System

  • Distributed Machine Learning, Federated Learning

  • LLM Inference/Serving System

  • AI/LLM Chip

Recent Research Projects

Federated Learning for Dynamic and Diverse Environments

• Communication-Efficient Federated Learning

• Security of Federated Learning (Backdoor Attack and Protection)

• Personalized Federated Learning

• Large-Scale Federated Learning Simulator and Platform

• Decision Tree Ensemble based Federated Learning

• Online Learning Algorithm/Accelerator

Domain-Specific Architecture and Machine Learning Accelerator

• DNN Training/Inference Accelerator (AI Chip)

• Hardware-Oriented DNN Algorithm (Quantized Neural Network, Binary Neural Network)

• Computation-Efficient Bayes Deep Learning Algorithm and Hardware

• Model Compression Algorithm for Hard-wired DNN Accelerators

• Hardware/Algorithm Co-design for Decision Tree Ensemble

• Accelerator for Multimodal AI and Robotics

Computer Architecture

• Secure Processor (Trusted Execution Environment; TEE)

• Memory Encryption and Integrity Verification

• Processing in Memory Circuit, Processor, and Compiler

• Energy-Efficient GPU Architecture

• Approximate Computing Architecture based on Stochastic Thermodynamics

Hardware Design Technology and Compiler

• Hardware Design Language and High-Level Synthesis Compiler

• Python-based Hardware Design Framework Veriloggen

• DNN Accelerator Synthesis Compiler NNgen 

• Hardware Description Obfuscation for IP Protection

• Covert Channel in Hardware Systems