Low-Power Versatile fe-nvm (多功能鐵電記憶體)

The next-generation non-volatile memory (NVM) requires low operating voltage and fast speed to save switching power (PS) for high-density memory application. However, further VD and PS reductions in a MOSFET are limited by the fundamental transistor physics of 60 mV/decade subthreshold swing (SS). The steep SS property not only lowers the PS but also reduces the DC off-state leakage. One proposed solution is to adopt ferroelectric MOSFET with a steep SS lower than 60 mV/dec. However, a weak ferroelectric polarization at a scaled thickness is not sufficient to prevent performance degradation on memory window, data retention and high-temperature endurance.