Digital Design of Clock and Buffer Products, 2023.01~ @Texas Instruments, ASC-DCC-CTS
Involved in various aspects of digital design such as RTL design, physical design, pre-silicon validation based on UVM.
Architecting and Design of Next Generation Deep Learning Accelerator, 2021.11~ @Micron Technology, AMS
Workload analysis to choose proper RISC-V processor for Micron's next generation DLA
Overall architecting Micron's next generation DLA focused Power/Performance/Area
Design of 5G Baseband Cellular Modem IP, 2019. 12 ~Present @Apple Mobile Deutschland
Developing and migrating legacy IPs for 5G baseband cellular modem
Design of 5G Baseband Cellular Modem, 2017. 08 ~ 2019. 12 @Intel Deutschland GmbH, iCDG
Developing memory subsystem for SRAM in 5G baseband cellular modem
Developing shared channel processor sub-block in 5G baseband cellular modem
OpenES Project (Open ESL Technologies for Next Generation Embedded Systems)@Verimag, Lab, 2015. 02 ~ 2015. 11
The goal of this project is to implement a simulation engine for formalism based on SystemC/TLM. The engine should allow co-simulating an abstract component with existing SystemC/TLM components. More specifically, we are trying to capture non-functional properties of a system such as power, temperature, etc at transaction level. Also, how to express non-determinisim in the simulation can be addressed in this project.
DeSyRe (On-Demand System Reliability) @University of Bristol, 2013. 8 ~ 2014. 04
The DeSyRe project performs research on the design of future reliable Systems-on-Chip (SoCs). These are systems that guarantee continuous and correct operation in the existence of different types of faults. At the increasing fault-rates, expected in the upcoming technology generations, DeSyRe will develop new design techniques for future SoCs, improving their reliability and reducing their power and performance overheads for fault-tolerance.
Energy-Aware Task Mapping Algorithm for 3-D IC based Network-on-Chip, Personal Research @Sogang University & @ University of Bristol, 2011.9 ~
3D IC is expected to give break-through to current planar 2D VLSI design methodology. TSV(Through-Silicon Via)'s superiority (lower power, higher performance) compared to global long wire can be efficiently used to network-on-chip design. To exploit the advantages of TSV of 3D ICs, new and efficient task mapping algorithm are required to maximize lower energy consumption of a system without sacrificing it performance.
Design of Efficient Asynchronous FIFO and MIPS Microprocessor, Personal Research @Hallym University, 2010. 10 ~ 2011. 9
Asynchronous circuits have been considered as an alternate solution to the high-power consumption, reliability of the synchronous circuits. In this work, we developed an efficient FIFO architecture, especially fitted to FPGA device. Also, we design an asynchronous MIPS processor which woks in Virtex-4 FPGA device. For the correct operation, we analyzed the gate and routing delay of the FPGA device and matched required delay for the bundled-data timing constraints.
Synthesis of Adaptable Hybrid Adders for Timing Optimization, Personal Research @SNU, 2009. 8 - 2010. 10
Satisfying the timing constraint is the utmost concern in the integrated circuit design. This work addresses the problem of redesigning the addition logic (in a form of hybrid adder) on a critical timing path to meet the timing constraint while minimally allocating the required addition logic. Unlike the conventional hybrid adder design schemes in which they assume uniform or specific patterns of input signal arrival times and minimize the latest timing of the output signals, our work extracts the required timing of each output signal as well as the input arrival times directly from the circuit.
Power-Delay Product Optimization of Heterogenous Adder (Extension of PhD Work), Personal Research @GIST, 2009. 3 - 2009. 8
- Adding power-delay measurement optimization methodology to PhD work. Power-delay product is direct indicator of energy consumed in a digital system. Using the technique to transform a non-linear expression to linear expression, an ILP model to optimize the power-delay product of the heterogeneous adder is developed.
Analysis of Open Source CAD Tool (BALSA) for Asynchronous Circuit Synthesis, funded by ETRI (Electronics and Telecommunication Research Institute in Korea), 2007. 7 - 2007. 11
- BALSA is a popular public-domain asynchronous CAD tool. In this project, we focused on modification of BALSA back-end flow to adopt a new commercial process technology. By the modification of BALSA back-end, a DI(Delay Insensitive)-style MSP430 micro-controller of TI (Texas Instruments) was designed as a case study.
Research on AES Core for Smart Card Robust to Differential Power Analysis Technique, funded by the Ministry of Information and Communication (Currently, Ministry of Knowledge and Economy) of Korea, 2002. 7. - 2004. 6.
- Asynchronous circuits are known to be robust to attacks such as SPA (simple power attack) or DPA(differential power attack) to H/W cryptographic systems due to its lack of clock signals. In this project, DPA-immune asynchronous AES were studied and developed.
Development of Asynchronous Design Technique for efficient IP integration in SOC, funded by Korea Research Foundation, 2002-2003
- In GALS (Globally Asynchronous and Locally Synchronous) environment, a clock-driven VLSI IP(Intellectual Property) is incorporated into that environment. The issues of synchronization, wrapper for local clock in GALS were addressed in this project.
Verilog Parser Development Project, funded by IPEAN (Currently, System Centroid), 2002.10 - 2003. 10
- To equip a verilog parser for web-based commercial CAD tool, “Flowrian”, in which synthesis and simulation are performed in server-side and the results are transported to client-side via the Internet, we developed a verilog parser engine for front-end of the synthesis tool.
SDL-C Translator Development Project, funded by ETRI, 2000. 3 -2001.2
SDL Parser Development for H/W-S/W Co-Design Environment Project, funded by ETRI, 1999. 3-1999.8
- With related to the above two projects, we adopted SDL(Specification and Description Language) as a system-level specification language for H/W-S/W co-design environment. SDL is an ITU-T standard specification language by which behaviors of communication protocol, real-time system, etc are described.