The paper titled "GALS Network-on-Chip Architecture for Power-Efficiency in FPGA Device", is accepted to 2012 IEEE/ACM Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems. I will attend the workshop from 5th Nov. 2012 ~ 8th Nov. 2012. It will be held at San Jose, USA and co-located with ICCAD 2012.