Embedded Files
Low-power IC Design:
Low-power IC Design:
In recent year, energy harvesting technologies from the ambient environments such as light, motion, wireless waves, and temperature again a lot of attraction form research community [1-5] due to its efficient solution in order to substitute for conventional power delivery methods, especially in wearable together with on-body applications. The drawbacks of battery-powered characteristic used in commodity applications lead to self-powered, long-lifetime circuit design. Thermoelectric generator, a solid-state sensor, is useful compared to the harvesting devices in order to enable self-sustained low-power applications. TEG based on the Seebeck effect is utilized to transfer thermal energy which is available with a temperature gradient into useful electrical energy. Depending on the temperature difference between two sides, amount of output power will be proportionally delivered. In this work, we illustrated a low-input voltage energy harvesting circuit applied discontinuous conduction mode (DCM) method for getting an adequate amount of energy from thermoelectric generator (TEG) for a specific wearable application. With a small temperature gradient harvested from human skin, the input voltage from the transducer is as low as 60mV, the proposed circuit, fabricated in a 0.6µm Nuvoton CMOS process, is capable of generating a regulated output voltage of 4.2V with an output power reaching to 40µW. The proposed circuit is useful for powering energy to battery-less systems, such as wearable application devices.
Research report: Thermoelectric Energy Harvesting Circuit With 60-mV Input Voltage
Memory Design:
Memory Design:
In-DRAM processing circuit is able to reduce operation time and power consumption than the traditional CPU+MEMORY system in performing the complicated computation such as convolution. These benefits are gained by bitwise and parallel processing of the in-DRAM convolution circuit. To realize the in-DRAM circuit, in this letter, we propose an inter-bank processing circuit with bitwise summation/comparison circuit for performing convolution inside DRAM. Compared to the intra-bank bitwise operation, the inter-bank circuit can significantly reduce the power consumption and the number of row activation cycles to accomplish convolution. For the number of cycles, the inter-bank circuit takes only 65 cycles for calculating 16×16 feature map. On the contrary, the intra-bank needs as many as 192 cycles. In terms of power consumption, the inter-bank circuit consumes smaller power by 35% than the intra-bank. In the proposed in-DRAM processing circuit, no complicated multiplier and adder are needed in performing the convolution. The MNIST recognition rate of the proposed bitwise processing circuit can be as high as 97.28%, indicating very little loss due to the ternary kernels.
Research Paper: In-DRAM bitwise processing circuit for low-power and fast computation (SCI)
Documents
Embedded System using FPGA download
Projects
Google Sites
Report abuse