Design module for a light-controlled lamp. 

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Report 1 , Report 2

Design of a NEC receiver. 

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Report 1 , Report 2

Design a LED controller with 2 brightness states.

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Report 1 , Report 2

Design of a NEC receiver. 

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Report 1 , Report 2

Design of a blackjack machine.. 

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Report 1 , Report 2

Design of a 2-bit free running counter. 

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Report 1 , Report 2 , Report 3 

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Report i -- feedback to student

Report 1 -- You have selected components from TSMC 0.18um technology. TSMC would be slower if we used 0.3um. So we give the full name of the process: TSMC 0.18um Process 1.8-Volt (page 5 delay section) You are downgraded by 3 pnts for not mentioning dynamic logic. 

Report 2 -- The gates contain transistors. So , transistor level design is not larger than gate level design. Transistor level design takes more "design time", so increases "engineering cost".  

Report 3 -- leakage power? * Changing Vth: you change the process itself, rather than changing width in the same process.  

-In dynamic CMOS circuit parasite capacities has a significant importance due to speed and power consumption. --> * speed and power consumption does not change parasitics. It is the other way around. Parasitic cap. affecting speed is less in dynamicCMOS, when compared to static CMOS; because we have a smaller pmos network in D.CMOS