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Students design and implement a simple multi-cycle central processing unit (CPU) that has a datapath unit and a hard-wired control unit which can process 8-bit data through various register transfers and Arithmetic Logic Unit (ALU) operations over a common 8-bit bus. Students write a comprehensive report explaining every single detail of their design and submit it along with the circuit source code.
multi-cycle central processing unit (CPU) DESIGN & IMPLEMENTATION
multi-cycle central processing unit (CPU) DESIGN & IMPLEMENTATION
In this project students worked in groups of two (three in exceptional circumstances like in case of odd/even enrollments in class etc). They are required to report what they have gone through/performed. The report and their performance evaluations by TAs are counted as the project's "written" part. The "action" part of the project is the demonstration session which was mandatory for the successful completion of their project.
Some examples of student reports explaining their designs can be found below.
Sample student report 1 from Fall 2020-2021
Sample student report 1 from Fall 2019-2021
Sample student report 1 from Fall 2018-2019
Sample student report 1 from Fall 2017-2018
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