MEC2067Syllabus

MEC2067 VHDL & VERILOG

Module -1:

Introduction to VHDL:

System design with uses, History of VHDL, Simulation fundamentals, Modelling hardware, and Language basics, Building blocks in VHDL, Design units and library.

Module -2:

Sequential Processing:

Process statement, Signal vs variable assignment, Sequential statements, For loop, While loop, Condition statements, Examples of half adder and full adder, Test bench.

Module -3:

Data Types and Subprograms:

Data types, Scalar, Composite, Access type, File type; Arrays; Objects, Signal variables, Constants and files, Association lists, Interface lists, Structural description, Examples. Subprogram, Functions, Conversion function, Resolution functions, Procedures.

Module -4:

Packages and VHDL Synthesis:

Packages, Package declaration, deferred constants, Subprogram declaration. Simple gate - concurrent assignment, IF control flow statement, Case control flow statement, Simple sequential statements, Asynchronous reset, Asynchronous preset and clear, Complex sequential statements.

Module -5:

Introduction to Verilog:

Synthesis and Synthesis in a design process, logic value system, Bit-widths, value holder and hardware modelling, Continuous assignment statement, Procedural assignment statement, Logical operator, arithmetic operator, relational operators, shift operators, vector operations, bit-selects, if statement, case statement, more on inferring latches, loop statement, Latch with preset and clear, modelling flip-flops, functions, tasks, gate level modelling.

Module -6:

Modelling:

Modelling of combinational, sequential logic and memory, Writing a Boolean expression, modelling a FSM and universal shift register, Modelling of a counter and ALU, modelling of parameterized adder, comparator and parity generator, Modelling of a decoder, multiplexer, and three state gate, factorial, UART, Blackjack model.

Module -7:

Model Optimizations and Verification

Resource allocation, common sub-expressions, moving code, common factoring, commutativity and associativity, flip-flop and latch optimizations, design size. A test bench, delays in assignment statements, unconnected ports, missing latches, More on delays, event list, synthesis directives, blocking and non-blocking assignments.

Text Books:

1. “VHDL” by Douglas Perry, TMH, 1999.

Reference Books:

1. VERILOG HDL SYNTHESIS, by J. Bhasker, BS Publication 2004.

2. Fundamental of Digital Logic with VERILOG DESIGN, by Stephen Brown I Zvonko

    Vranesic, The McGraw-Hill Companies.

3. VERILOG HDL, A Guide to Digital Design and Synthesis, by Prabhu Goel,