Laboratory journal is to be prepared using following template for experiments performed in MEC1004 VLSI Design Lab

1. Aim of the experiment: – Design a CMOS inverter having equal t_PLH (low to high) (or positive) output transition and t_PHL (high to low) (or negative) transition .Take reading of t_PLH and t_PHL and tabulate the same against W_p (width of PMOSFET) (take L_n =L_p = 45 nm) for estimation of t_P (propagation delay).

2. CAD Tools used: Virtuoso Analog Design Environment of cadence.

3. Theory:

(i) Diagram :

(iii) Explanation: A combinational circuit that performs an addition of two 4-bit binary numbers in parallel is called a 4-bit ripple carry full adder. This circuit can be implemented using four 1-bit full adders (give the gate-level diagram of 1-bit full adder and block diagram of 4-bit ripple carry full adder). The bits of the input binary numbers designate the augend and addend bits whereas the output binary number is the 4-bit sum and a 1-bit carry.

4. Procedure:

Write down the Verilog source code required to implement the prescribed behaviour of the given circuit or describe the procedure for performing the experiment using Xilinx/Virtuoso ADE.

5. Observation table:

6. Results/waveforms: to be drawn/printed (snap shot)

7. Remarks/Conclusion (if any): - t_PLH = t_PLH is achieved at Wp = 180 ns.

8. Precautions to be taken (if any):