Patents

[P9] R. S. Ghaida and S. Muddu, "Selection of replacement patterns for reducing manufacturing hotspots and constraint violations of IC designs," US Patent no. 8869077, GlobalFoundries assignee, Granted, October 2014.

[P8] S. Muddu and R. S. Ghaida, "Pattern-based replacement for layout regularization," US Patent no. 8826197, GlobalFoundries assignee, Granted, September 2014.

[P7] P. Pathak and R. S. Ghaida, "Context-Aware Pattern Optimization," Protected as Trade Secret by GlobalFoundries, March 2014.

[P6] R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, and S. R. Nassif, "Multiple patterning layout decomposition for ease of conflict removal," US Patent no. 8516403, IBM assignee, Granted, Aug. 2013.

[P5] R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, and S. R. Nassif, "Mask assignment for multiple patterning lithography," US Patent no. 8434033, IBM assignee, Granted, Apr. 2013.

[P4] P. Gupta and R. S. Ghaida, "Single mask double-patterning lithography," US Patent no. 8415089, UCLA assignee, Granted, in Apr. 2013.

[P3] R. S. Ghaida and K. B. Agarwal, "Resolving double patterning conflict," US Patent no. 8359556, IBM assignee, Granted, Jan. 2013.

[P2] R. S. Ghaida, A. Mohieldin, S. Muddu, P. Pathak, V. Dai, and L. Capodieci, "Design layout pattern correction for integrated circuits," Pending, filed by GlobalFoundries in Oct. (2013).

[P1] R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, and S. R. Nassif, "Dynamic pin-access maximization for multi-patterning lithography," US Patent Application, No. 20130159955, filed by IBM in Dec. (2011).