Journal Papers

(Refereed)

Listed files may slightly differ in content from the published versions (Copyright note)

[J1] R. S. Ghaida, M. Gupta, and P. Gupta, "Framework for exploring the interaction between design rules and overlay control," SPIE Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 12(3), pp. 033014-1 033014-11, Aug. (2013). [PDF]

[J2] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. Liebmann, and P. Gupta, "Layout decomposition and legalization for double-patterning technology," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), DOI 10.1109/TCAD.2012.2232710, vol. 32(2), pp. 202-215, Feb. (2013). [PDF]

[J3] R. S. Ghaida and P. Gupta, "DRE: a framework for early co-evaluation of design rules, technology choices, and layout methodologies," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), DOI 10.1109/TCAD.2012.2192477, vol. 31(9), pp. 1379-1392, Sept. (2012). [PDF]

[J4] R. S. Ghaida, G. Torres, and P. Gupta, "Single-mask double-patterning lithography for reduced cost and improved overlay control," IEEE Trans. On Semiconductor Manufacturing (TSM), DOI 10.1109/TSM.2010.2076305, vol. 24(1), pp. 381-390, Feb. (2011). [PDF]

[J5] R. S. Ghaida and P. Gupta, "Within-layer overlay impact for design in metal double patterning," IEEE Trans. On Semiconductor Manufacturing (TSM), DOI 10.1109/TSM.2010.2050157, vol. 23(3), pp. 381-390, Aug. (2010). [PDF]

[J6] R. S. Ghaida, K. Doniger, and P. Zarkesh-Ha, "Random yield prediction based on a stochastic layout sensitivity model," IEEE Trans. On Semiconductor Manufacturing (TSM), DOI 10.1109/TSM.2009.2024821, vol. 22(3), pp. 329-337, Aug. (2009). [PDF]

[J7] R. S. Ghaida and P. Zarkesh-Ha, "A layout sensitivity model for estimating electromigration-vulnerable narrow interconnects," Journal of Electronic Testing: Theory and Apps. (JETTA), DOI 10.1007/s10836-008-5079-x, vol. 25(1), pp. 67-77, Feb. (2009). [PDF]