Conference Papers

(Peer-Reviewed unless Invited)

Listed files may slightly differ in content from the published versions (Copyright note)

[C14] R. S. Ghaida, Y. Badr, and P. Gupta, "Pattern-restricted design at 10nm and beyond," IEEE International Conference on Computer Design (ICCD), Oct. 2014. (Invited) [PDF]

[C13] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, "Comprehensive die-level assessment of design rules and layouts,'" IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 61 - 66, Jan. (2014). [PDF]

[C12] R. S. Ghaida and P. Gupta, "Role of design in multiple patterning: technology development, design enablement and process control," IEEE Design Automation and Test in Europe (DATE), pp. 314 - 319, Mar. (2013). [PDF] (Invited)

[C11] R. S. Ghaida, M. Gupta, and P. Gupta, "A framework for exploring the interaction between design rules and overlay control," SPIE Advanced Lithography -- Metrology, Inspection, and Process Control for Microlithography, vol. 8681, pp. 86810C-86810C-12, Feb. (2013). [PDF]

[C10] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, "A methodology for the early evaluation and exploration of double-patterning design rules," IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD), pp. 50 - 56, Nov. (2012). [PDF]

[C9] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, "O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction," IEEE Intl. Conf. on Integrated Circuit Design and Technology (ICICDT), pp. 1 - 4, Jun. (2012). [PDF] (Invited)

[C8] R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, S. R. Nassif, and P. Gupta, "A novel methodology for triple/multiple-patterning layout decomposition," SPIE Advanced Lithography -- Design for Manufacturability through Design-Process Integration, vol. 8327, pp. 83270M-83270M-8, Feb. (2012). [PDF]

[C7] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, "A framework for double patterning-enabled design," IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD), pp. 14-20, Nov. (2011). [PDF]

[C6] A. R. Neureuther, J. Rubinstein, M. Miller, K. Yamazoe, E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T.-J. King Liu, X. Sun, K. Jeong, P. Gupta, A. Kaqalwalla, R. S. Ghaida, T.-B. Chan, "Collaborative research on emerging technologies and design," SPIE Photomask Japan -- Photomask and Next-Generation Lithography Mask Technology, vol. 8081, pp. 80810N-80810N-7, Apr. (2011). [PDF] (Invited)

[C5] T.-B. Chan, R. S. Ghaida, and P. Gupta, "Electrical modeling of lithographic imperfections," IEEE Intl. Conference on VLSI Design (VLSI Design), pp. 423-428, Jan. (2010). [PDF] (Invited)

[C4] R. S. Ghaida and P. Gupta, "A framework for early and systematic evaluation of design rules," IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD), pp. 615-622, Nov. (2009). [PDF]

[C3] R. S. Ghaida, G. Torres, and P. Gupta, "Single-mask double-patterning lithography," SPIE Photomask Technology, vol. 7488, pp. 74882J-74882J-11, Sept. (2009). [PDF]

[C2] R. S. Ghaida and P. Gupta, "Design-overlay interactions in metal double patterning," SPIE Advanced Lithography -- Design for Manufacturability through Design-Process Integration, vol. 7275, pp. 727514-727514-10, Feb. (2009). [PDF]

[C1] R. S. Ghaida and P. Zarkesh-Ha, "Estimation of electromigration-aggravating narrow interconnects using a layout sensitivity model," IEEE Intl. Symp. on Defect and Fault-Tolerance in VLSI Systems (DFT'07), pp. 59-67, Sept. 2007. [PDF]