Publications

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Refereed Journal Papers

[J7] R. S. Ghaida, M. Gupta, and P. Gupta, "Framework for exploring the interaction between design rules and overlay control," SPIE Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 12(3), pp. 033014-1 033014-11, Aug. (2013). [PDF]

[J6] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. Liebmann, and P. Gupta, "Layout decomposition and legalization for double-patterning technology," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), DOI 10.1109/TCAD.2012.2232710, vol. 32(2), pp. 202-215, Feb. (2013). [PDF]

[J5] R. S. Ghaida and P. Gupta, "DRE: a framework for early co-evaluation of design rules, technology choices, and layout methodologies," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), DOI 10.1109/TCAD.2012.2192477, vol. 31(9), pp. 1379-1392, Sept. (2012). [PDF]

[J4] R. S. Ghaida, G. Torres, and P. Gupta, "Single-mask double-patterning lithography for reduced cost and improved overlay control," IEEE Trans. On Semiconductor Manufacturing (TSM), DOI 10.1109/TSM.2010.2076305, vol. 24(1), pp. 381-390, Feb. (2011). [PDF]

[J3] R. S. Ghaida and P. Gupta, "Within-layer overlay impact for design in metal double patterning," IEEE Trans. On Semiconductor Manufacturing (TSM), DOI 10.1109/TSM.2010.2050157, vol. 23(3), pp. 381-390, Aug. (2010). [PDF]

[J2] R. S. Ghaida, K. Doniger, and P. Zarkesh-Ha, "Random yield prediction based on a stochastic layout sensitivity model," IEEE Trans. On Semiconductor Manufacturing (TSM), DOI 10.1109/TSM.2009.2024821, vol. 22(3), pp. 329-337, Aug. (2009). [PDF]

[J1] R. S. Ghaida and P. Zarkesh-Ha, "A layout sensitivity model for estimating electromigration-vulnerable narrow interconnects," Journal of Electronic Testing: Theory and Apps. (JETTA), DOI 10.1007/s10836-008-5079-x, vol. 25(1), pp. 67-77, Feb. (2009). [PDF]

Conference Papers (Peer-Reviewed unless Invited)

[C14] R. S. Ghaida, Y. Badr, and P. Gupta, "Pattern-restricted design at 10nm and beyond," IEEE International Conference on Computer Design (ICCD), Oct. 2014. (Invited) [PDF]

[C13] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, "Comprehensive die-level assessment of design rules and layouts,'" IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 61 - 66, Jan. (2014). [PDF]

[C12] R. S. Ghaida and P. Gupta, "Role of design in multiple patterning: technology development, design enablement and process control," IEEE Design Automation and Test in Europe (DATE), pp. 314 - 319, Mar. (2013). [PDF] (Invited)

[C11] R. S. Ghaida, M. Gupta, and P. Gupta, "A framework for exploring the interaction between design rules and overlay control," SPIE Advanced Lithography -- Metrology, Inspection, and Process Control for Microlithography, vol. 8681, pp. 86810C-86810C-12, Feb. (2013). [PDF]

[C10] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, "A methodology for the early evaluation and exploration of double-patterning design rules," IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD), pp. 50 - 56, Nov. (2012). [PDF]

[C9] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, "O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction," IEEE Intl. Conf. on Integrated Circuit Design and Technology (ICICDT), pp. 1 - 4, Jun. (2012). [PDF] (Invited)

[C8] R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, S. R. Nassif, and P. Gupta, "A novel methodology for triple/multiple-patterning layout decomposition," SPIE Advanced Lithography -- Design for Manufacturability through Design-Process Integration, vol. 8327, pp. 83270M-83270M-8, Feb. (2012). [PDF]

[C7] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, "A framework for double patterning-enabled design," IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD), pp. 14-20, Nov. (2011). [PDF]

[C6] A. R. Neureuther, J. Rubinstein, M. Miller, K. Yamazoe, E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T.-J. King Liu, X. Sun, K. Jeong, P. Gupta, A. Kaqalwalla, R. S. Ghaida, T.-B. Chan, "Collaborative research on emerging technologies and design," SPIE Photomask Japan -- Photomask and Next-Generation Lithography Mask Technology, vol. 8081, pp. 80810N-80810N-7, Apr. (2011). [PDF] (Invited)

[C5] T.-B. Chan, R. S. Ghaida, and P. Gupta, "Electrical modeling of lithographic imperfections," IEEE Intl. Conference on VLSI Design (VLSI Design), pp. 423-428, Jan. (2010). [PDF] (Invited)

[C4] R. S. Ghaida and P. Gupta, "A framework for early and systematic evaluation of design rules," IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD), pp. 615-622, Nov. (2009). [PDF]

[C3] R. S. Ghaida, G. Torres, and P. Gupta, "Single-mask double-patterning lithography," SPIE Photomask Technology, vol. 7488, pp. 74882J-74882J-11, Sept. (2009). [PDF]

[C2] R. S. Ghaida and P. Gupta, "Design-overlay interactions in metal double patterning," SPIE Advanced Lithography -- Design for Manufacturability through Design-Process Integration, vol. 7275, pp. 727514-727514-10, Feb. (2009). [PDF]

[C1] R. S. Ghaida and P. Zarkesh-Ha, "Estimation of electromigration-aggravating narrow interconnects using a layout sensitivity model," IEEE Intl. Symp. on Defect and Fault-Tolerance in VLSI Systems (DFT'07), pp. 59-67, Sept. 2007. [PDF]

Workshop Papers

[W2] R. S. Ghaida, M. Gupta, and P. Gupta, "A framework for exploring the interaction between design rules and overlay control," IEEE Intl. Workshop on Design for Manufacturability and Yield (DFM&Y), Jun. 2012. [PDF]

[W1] R. S. Ghaida and P. Gupta, "A framework for systematic evaluation and exploration of design rules," SRC TECHCON Conference, Sept. (2009). [PDF]

Software

[S1] R. S. Ghaida, UCLA Design Rule Evaluator, [Online]. Available: http://nanocad.ee.ucla.edu/Main/DownloadForm, (2009--12).

Theses

[T3] R. S. Ghaida, "Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies," University of California, Los Angeles, PhD Dissertation, Sept. (2012). [PDF]

[T2] R. S. Ghaida, "Semiconductor yield analysis and prediction using a stochastic layout sensitivity model," University of New Mexico, Master's Thesis, May (2008). [PDF]

[T1] R. S. Ghaida, "A Different Approach to Fabricating Three-Dimensional Integrated Circuits," Lebanese American University, Undergraduate Thesis, Oct. (2005). [PDF brief]

Patents

[P9] R. S. Ghaida and S. Muddu, "Selection of replacement patterns for reducing manufacturing hotspots and constraint violations of IC designs," US Patent no. 8869077, GlobalFoundries assignee, Granted, October 2014.

[P8] S. Muddu and R. S. Ghaida, "Pattern-based replacement for layout regularization," US Patent no. 8826197, GlobalFoundries assignee, Granted, September 2014.

[P7] P. Pathak and R. S. Ghaida, "Context-Aware Pattern Optimization," Protected as Trade Secret by GlobalFoundries, March 2014.

[P6] R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, and S. R. Nassif, "Multiple patterning layout decomposition for ease of conflict removal," US Patent no. 8516403, IBM assignee, Granted, Aug. 2013.

[P5] R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, and S. R. Nassif, "Mask assignment for multiple patterning lithography," US Patent no. 8434033, IBM assignee, Granted, Apr. 2013.

[P4] P. Gupta and R. S. Ghaida, "Single mask double-patterning lithography," US Patent no. 8415089, UCLA assignee, Granted, in Apr. 2013.

[P3] R. S. Ghaida and K. B. Agarwal, "Resolving double patterning conflict," US Patent no. 8359556, IBM assignee, Granted, Jan. 2013.

[P2] R. S. Ghaida, A. Mohieldin, S. Muddu, P. Pathak, V. Dai, and L. Capodieci, "Design layout pattern correction for integrated circuits," Pending, filed by GlobalFoundries in Oct. (2013).

[P1] R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, and S. R. Nassif, "Dynamic pin-access maximization for multi-patterning lithography," US Patent Application, No. 20130159955, filed by IBM in Dec. (2011).