Projects (before 2015)

Pattern Optimizer (POP)

A revolutionary database-driven computational infrastructure for layout-pattern optimization and pattern-based layout construction [ICCD'14]. POP promises to transform layout creation from a create-then-fix approach, which is bound to break in future technology nodes, into a correct-by-construction approach where layout is built out of pre-certified pattern parts. A basic version of the system has been successfully deployed into GlobalFoundries' tapeout flow to apply pattern-based lithography-hotspots fixing and generic yield-enhancing layout modifications. This work produced three granted patents [P1, P2, P9], which were supported by GlobalFoundries.

Design Rules Evaluator (DRE)

A first-of-its-kind computational infrastructure (DRE) for fast and systematic evaluation of design rules, technology choices, and layout methodologies at early stages of technology development. The infrastructure is used by researchers from 23 universities and 12 top-notch industry R&D centers. For designers, DRE is a means to avoid unforeseen disruptions of future nanotechnology. For technologists, DRE is a means to evaluate alternative nanotechnologies from the perspective of improving key circuit-design metrics. See publications [TCAD'12, ICCAD'09, ICCAD'12, SPIE'13, JM3'13, ASPDAC'14].

Layout decomposition for multiple-patterning technology

O(n) heuristic algorithm for the layout decomposition of double-patterning [ICCAD'11, TCAD'13] with extension for triple-patterning [SPIE'12]. The double-patterning algorithm is the fastest among the many available layout decomposition algorithms and achieves a violation-free coloring solution when one exists. The triple-patterning algorithm was one of the first works on this topic and the very first to leverage triple-patterning-specific stitching capability, which greatly helps in achieving a legal decomposition solution. The method, for which IBM was granted a patent [P5], became part of IBM’s internal coloring solution and was transferred to Mentor Graphics.

Layout legalization for multiple-patterning technology

A general methodology for the automatic adaptation of layouts to double-patterning technology [ICCAD'11, TCAD'13], which can be applied for double/triple-patterning as well as self-aligned double-patterning technology. This legalization is performed simultaneously across all layout layers using a compactor and while minimizing layout perturbations. Our layout-compaction formulation of the problem allowed for high-quality results with extremely fast run-time (few seconds for cells, few minutes for macros). This work produced two granted patents [P4, P7], which were supported by IBM.

Overlay electrical impact in multiple-patterning technology

A method to analyze design-level electrical impact of overlay in MP and the relative importance of the different components of overlay [SPIE'09, TSM'10]. The method can be used to bring design-awareness into process decision-making, thereby advancing more design-friendly manufacturing and reducing overlay-control requirements.

Single-mask multiple-patterning technology

A novel technique for MP manufacturing that uses a single mask for multiple exposures [BACUS'09, TSM'11]. We demonstrated the method application on bidirectional layouts and its benefits over conventional MP in terms of mask-cost, manufacturing throughput, and process control. This work produced a granted patent [P4] supported by UCLA, in conjunction with the Semiconductor Research Corporation.

Stochastic yield prediction for hard and soft particle defects

A methodology to model and predict random yield with high fidelity based on a stochastic layout sensitivity model that uses basic layout information [TSM'09], enabling pre-layout yield forecasting for future technology generations. We extended the layout sensitivity model to estimate the probability of soft defects [DFT'07, JETTA'09] and predict mean-time-to-failure and yield in future technologies.