5- Finite State Machines

Learning outcomes: Explain the distinctive feature of finite state machines and how they differ from regular sequential circuits | Explain the difference between Mealy and Moore FSM | Create a state diagram and the VHDL design file and source simulation for a simple FSM

slides | script | podcast (cf. errata for presentation 5a

Files: 5-bit sequence detector: design - simulation

Learning outcomes: Represent the behavior of a finite state machine using a state transition diagram or algorithmic state machine (ASM) chart | Convert a state transition diagram or ASM chart into an equivalent VHDL description

slides | script | podcast (cf. errata for presentation 5b)

Files: 5-bit sequence detector: design

Learning outcomes: Explain the functional requirements of the e-dice | Plan the tasks needed to implement a solution using Vivado

slides | script | podcast (cf. errata for presentation 5c)

(a brief demo of a student's implementation of the FSM-based e-dice)

(no slides) | script | podcast