Learning outcomes: Explain what are the distinctive features of sequential circuits and regular sequential circuits | Describe regular sequential circuit structures using VHDL
slides | script | podcast (cf. errata for presentation 4a)
Files: 8-bit register design | 8-bit shift-left register design | 8-bit U/D counter design
Learning outcomes: Explain how to expand the simulation source file to consider the existence of the clock signal | Write test bench files for regular sequential circuits
Files: 8-bit register design - simulation | 8-bit shift-left register design- simulation | 8-bit U/D counter design- simulation