Learning goals: Explain the basic rules governing the use of VHDL | Explain why VHDL is intrinsically concurrent | Distinguish between concurrent and sequential statements
Files: 2:4 decoder design - simulation - constraints
Learning goals: Explain what are the main sections of a VHDL description file (library, entity, architecture) | Explain the differences between dataflow, behavioral and structural modelling styles (architecture section)
Files: 2:4 dec dataflow design - simulation - constraints | 2:4 dec behav A design - simulation - constraints | 2:4 behav B design - simulation - constraints | 2:4 struct A design | simulation - constraints | 2:4 struct B design - simulation | constraints | N.B.: The structural descriptions need the lower-level 2:4 decoder design file.
Learning goals: Explain the relation between the IEEE library packages std_logic_1164 and numeric_std, and some commonly used data types and operators | Explain what is type casting and why it is necessary
Files: 4-bit adder design - simulation - constraints
Learning goals: Describe the most common concurrent statements and the most common sequential statements | Explain how they can be used
slides | script | podcast (cf. errata for presentation 2d)
Files: Concurrent statements Signal assignment: design - simulation - constraints | Conditional: design - simulation - constraints | Selected: design - simulation - constraints | Sequential statements Signal assignment: design - simulation - constraints | If: design - simulation - constraints | Case: design - simulation - constraints
Learning goals: Explain what are the main architectural building blocks in a Xilinx FPGA | List the resources available in the configurable logic blocks | Explain what resources were required to implement a 2:4 decoder
Files: 2:4 decoder design - simulation - constraints
External: Xilinx UG474 user guide