Learning outcomes: Explain what are combinational circuits and what is their main limitation | Compare dataflow, behavioral, structural design styles in the case of combinational circuits | Compare combinational circuit implementations using concurrent and sequential statements
slides | script | podcast (cf. errata for presentation 3a)
Files: Concurrent dataflow: design - simulation - constraints | Concurrent behavioral A (when/else): design - simulation - constraints | Concurrent behavioral B (with/select): design - simulation - constraints | Sequential dataflow: design - simulation - constraints | Sequential if: design - simulation - constraints | Sequential case: design - simulation - constraints | Structural A: design - simulation - constraints | Structural B: design - simulation - constraints [N.B.: The structural descriptions need the lower-level 2:4 decoder design file]
Learning outcomes: Explain what is design verification and how it can be achieved by simulation | Create simulation sources in the form of VHDL description files using Process statements
Files: 2:4 decoder: design | simulation | constraints