#corresponding author, *first author
2025
[xx] J. Kim*, ~ ~, and SY Woo#, "Diode-Type 3D NAND Flash Memory ~ ", (In Prep.-Writing)
[xx] J. Im*, ~ ~, and SY Woo#, "XNOR ~ High Density ~ ", (In Prep.-Writing)
[xx] J. Gu*, ~ ~, and SY Woo#, "Proton Radiation ~ ", (In Prep.-Writing)
[xx] W. Song*, ~ ~, and SY Woo#, "Thyristor 1T-DRAM ~ ", (In Prep.-Writing)
[xx] T. Kwon*, ~ ~, and SY Woo#, "A CMOS-based Ternary Inverter ~ ", (In Prep.-Writing)
[xx] J. Im*, J. Im, J. Ko, J. Kim, W. Shin, R.-H. Koo, S.-H. Park, SY Woo#, and J-H Lee#, "Harnessing Chaotic Bifurcation ~", Nature Communication (In Revision-Peer Review)
[41] Hansol Kim*, Jisung Im, Jinsu Kim, Taesung Kwon, Yoonki Hong, Dongkyu Jang, Sung Yun Woo#, "Extended Single-sided Row Hammer in DRAM: Concept and Physical Mechanism Analysis", IEEE Electron Device Letters, xx (xx), 1-8. (2025/9/2) (IF: 4.5)
[40] Jinsu Kim*, Hansol Kim, Jisung Im, Sung-Tae Lee, Dongseok Kwon, Nagyong Choi, Sung Yun Woo#, "Comparative Analysis of Grain Boundary Effects in FET-Type and Diode-Type 3D NAND Flash Memory", IEEE Transactions on Electron Devices, 72 (10), 5428-5435. (2025/10/1) (IF: 3.2)
[39] Tae Seong Kwon*, Young Jun Yoon, Do Yeon Park, Jong-Ho Bae, Young Suh Song, Hyoung Woo Kim, Jae Hwa Seo#, Sung Yun Woo#, "Structurally Optimized SiC CMOS FinFET for High-Temperature and Low-Power SoC Logic Integration", Scientific Reports, 15 (28158), 1-12. (2025/8/1) (IF: 3.9 & JCR: 18.1%)
[38] Jonghyun Ko*, Jiseong Im*, Jangsaeng Kim, Wonjun Shin, Ryun-Han Koo, Sung-Ho Park, Sung Yun Woo#, Jong-Ho Lee #, "CMOS-compatible flash-gated thyristor–based neuromorphic module with small area and low energy consumption for in-memory computing", Science Advances, 11 (29), 1-8. (2025/7/18) (IF: 12.5 & JCR: 8.5%)
[37] Yoonki Hong*, Jonghyun Yun, Dongjin Han, Sung-Tae Lee, Sung Yun Woo#, "Sensing Characteristics and Transduction Mechanism of WO3-based Si FET-type Humidity Sensor Using Pulse Measurement ", JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 25 (3), 325-334. (2025/6/1)
[36] Jisung Im*, Sangyeon Pak, Sung Yun Woo#, Wonjun Shin#, Sung-Tae Lee#, "Flash Memory for Synaptic Plasticity in Neuromorphic Computing: A Review ", Biomimetics 10 (2), 121. (2025/2/18) (IF: 3.9)
[35] Jisung Im*, Hansol Kim, Hyungjin Kim#, Sung Yun Woo#, "Design Strategies for BCAT Structures: Enhancing DRAM Reliability and Mitigating Row Hammer Effect ", Electronics, 14, 3, 499. (2025/1/26) (IF: 2.6)
[34] Dongkyu Jang*, Taehoon Park, Inkyum Lee, Jongkyu Kim, Sang Bin Ahn, Jieun Lee, Shindeuk Kim, Hyodong Ban, Sung Yun Woo, Yoonki Hong#, "Gate oxide technology relieving word-line break in 10 nm-class DRAMs ", Japanese Journal of Applied Physics, 64, 1, 01SP04. (2025/1/7) (IF: 1.8)
2024
[33] Hansol Kim*, Sung Yun Woo#, Hyungjin Kim#, "Neuron Circuit Based on a Split-gate Transistor with Nonvolatile Memory for Homeostatic Functions of Biological Neurons", Biomimetics 9 (6), 335 (2024/5/31) (IF: 3.9)
[32] Min-Kyu Park*, Joon Hwang*, Kyung Min Lee, Sung Yun Woo, Jae-Joon Kim, Jong-Ho Bae#, Jong-Ho Lee#, "Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training", Advanced Electronic Materials, 2300866. (2024/4/1) (IF: 5.3)
[31] Sung Yun Woo*, Sangyeon Pak, Sung-Tae Lee#, "Deep Spiking Neural Networks with Integrate and Fire Neuron Using Steep Switching Device ", Solid-State Electronics, 108860. (2024/1/12) (IF: 1.4)
2023
[30] D Kwon*, SY Woo, J Hwang, H Kim, JH Bae, W Shin, BG Park, JH Lee#, "Efficient Hybrid Training Method for Neuromorphic Hardware Using Analog Nonvolatile Memory", IEEE Transactions on Neural Networks and Learning Systems, 1-13. (IF: 8.9 & JCR: 4.2%)
[29] K-H Lee*, D Kwon*, I-S Lee, J Hwang, J Im, JH Bae, W Y Choi, SY Woo#, JH Lee#, "Si-Based Dual-Gate Field-Effect Transistor Array for Low-Power On-Chip Trainable Hardware Neural Networks", Advanced Intelligent Systems, 2300490. (IF: 6.8 & JCR: 10.1%)
[28] D Kwon*, SY Woo#, KH Lee, J Hwang, H Kim, S-H Park, W Shin, JH Bae, JH Lee#, "Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons", Science Advances 9 (29), 1-8. (IF: 11.7 & JCR: 7.8%)
[27] D Kwon*, H Kim, KH Lee, J Hwang, W Shin, JH Bae, SY Woo#, JH Lee#, "Super-steep synapses based on positive feedback devices for reliable binary neural networks", Applied Physics Letters 122 (10), 102101. (IF: 3.6)
[26] S Lee*, S Oh, SY Woo, BG Park, JH Lee#, "Synaptic array using multi-level AND flash memory cells for hardware-based neural networks ", Solid-State Electronics, 200, 108566. (IF: 1.4)
[25] SY Woo*, D Kwon, BG Park, JH Lee#, JH Bae#, "Demonstration of Pulse Width Modulation Function Using Single Positive Feedback Device for Neuron", IEEE Electron Device Letters 44 (1), 5-8. (IF: 4.1)
2022
[24] SY Woo*, WM Kang, YT Seo, S Lee, D Kwon, S Oh, JH Bae, JH Lee#, "Demonstration of integrate-and-fire neuron circuit for spiking neural networks" Solid-State Electronics 198, 108481.
[23] KH Lee*, D Kwon*, SY Woo, JH Ko, WY Choi, BG Park, JH Lee#, "Highly Linear Analog Spike Processing Block Integrated With an AND-Type Flash Array and CMOS Neuron Circuits", IEEE Transactions on Electron Devices 69 (11), 6065-6071.
[22] D Kwon*, SY Woo*, JH Lee#, "Review of Analog Neuron Devices for Hardware-based Spiking Neural Networks", JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 22 (2), 115-131.
[21] S Oh*, D Kwon, G Yeom, WM Kang, S Lee, SY Woo, J Kim, JH Lee#, "Neuron Circuits for Low-Power Spiking Neural Networks Using Time-To-First-Spike Encoding",IEEE Access 10, 24444-24455.
[20] H Kim*, SY Woo, S Lee, YT Seo, BG Park, JH Lee#, "Variation-Tolerant Capacitive Array for Binarized Neural Network", IEEE Electron Device Letters 43 (3), 478-481.
2021
[19] MK Park*, HN Yoo, J Hwang, SY Woo, D Kwon, YT Seo, JH Lee, JH Bae#, "CMOS-compatible low-power gated diode synaptic device for hardware-based neural network",
IEEE Transactions on Electron Devices 69 (2), 832-837.
[18] D Kwon*, SY Woo*, JH Bae, S Lim, BG Park, JH Lee#, "Hardware-based spiking neural networks using capacitor-less positive feedback neuron devices" IEEE Transactions on Electron Devices 68 (9), 4766-4772.
[17] J Kim*, D Kwon, SY Woo, WM Kang, S Lee, S Oh, CH Kim, JH Bae, JH Lee#, "On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm", Neural Computing and Applications 33, 9391-9402.
[16] YT Seo*, D Kwon*, Y Noh, S Lee, MK Park, SY Woo, BG Park, JH Lee#, "3-D AND-type flash memory architecture with high-κ gate dielectric for high-density synaptic devices", IEEE Transactions on Electron Devices 68 (8), 3801-3806.
[15] S Oh*, S Lee, SY Woo, D Kwon, J Im, J Hwang, JH Bae, BG Park, JH Lee#, "Spiking Neural Networks With Time-to-First-Spike Coding Using TFT-Type Synaptic Device Model", IEEE Access 9, 78098-78107.
[14] WM Kang*, D Kwon*, SY Woo, S Lee, H Yoo, J Kim, BG Park, JH Lee#, "Hardware-based spiking neural network using a TFT-type AND flash memory array architecture based on direct feedback alignment", IEEE Access 9, 73121-73132.
[13] JW Back*, MK Park, HN Yoo, JH Bae, SY Woo, BG Park, JH Lee#, "Variability of DRAM Peripheral Transistor at Liquid Nitrogen Temperature" IEEE Transactions on Electron Devices 68 (4), 1627-1632.
[12] J Kim*, D Kwon, SY Woo, WM Kang, S Lee, S Oh, CH Kim, JH Bae, JH Lee#, "Hardware-based spiking neural network architecture using simplified backpropagation algorithm and homeostasis functionality", Neurocomputing 428, 153-165.
2020
[11] SY Woo*, D Kwon*, N Choi, WM Kang, YT Seo, MK Park, JH Bae, BG Park, JH Lee#, "Low-power and high-density neuron device for simultaneous processing of excitatory and inhibitory signals in neuromorphic systems", IEEE Access 8, 202639-202647.
[10] ST Lee*, SY Woo*, JH Lee*, "Low-power binary neuron circuit with adjustable threshold for binary neural networks using NAND flash memory" , IEEE Access 8, 153334-153340.
[9] SY Woo*, KB Choi, J Kim, WM Kang, CH Kim, YT Seo, JH Bae, BG Park, JH Lee#, "Implementation of homeostasis functionality in neuron circuit using double-gate device for spiking neural network ", Neural Computing and Applications 33, 9391-9402.
[8] J Kim*, CH Kim, SY Woo, WM Kang, YT Seo, S Lee, S Oh, JH Bae, BG Park, JH Lee#, "Initial synaptic weight distribution for fast learning speed and high recognition rate in STDP-based spiking neural network", Solid-State Electronics 165, 107742.
2019
[7] MK Park*, HN Yoo, YT Seo, SY Woo, JH Bae, BG Park, JH Lee#, "Field effect transistor-type devices using high-κ gate insulator stacks for neuromorphic applications ", ACS Applied Electronic Materials 2 (2), 323-328.
[6] JH Bae*, JW Back, MW Kwon, JH Seo, K Yoo, SY Woo, K Park, BG Park, JH Lee#, "Characterization of a capacitorless DRAM cell for cryogenic memory applications" , IEEE Electron Device Letters 40 (10), 1614-1617.
[28] DArrays and Super-Steep Neurons", Sci