Research

Research Area

• PVT variation tolerant and low power circuit design for Memory & MCU (memory read/write circuit, F/F, logic, ALU, CAM, normally-off computing) 

• High security level circuit design for MCU (RNG, PUF) 

• Ultra-low power analog front end (AFE) and digital back end (DBE) circuit design for IoT applications

• Deep learning neuromorphic SoC, in-memory computing (IMC), compute-in-memory (CIM), PIM, etc.

Research Highlight

• Ternary output binary neural network with zero-skipping for MRAM-based digital in-memory computing

IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II). Jul. 2023.

This paper presents a novel ternary output binary neural network (BNN) and an MRAM-based digital in-memory computing (IMC) architecture. The proposed ternary output BNN and IMC architecture is capable of 1) improving array efficiency by using only one bit-cell for one synaptic weight, 2) no accuracy loss due to its digital nature, 3) high energy efficiency by employing a zero-skipping scheme, and 4) the use of normal memory and deep learning applications due to minimized array modification. System simulations with a two-layer perceptron show that the ternary output BNN achieves 92.12% inference accuracy measured against the MNIST dataset, while the conventional BNN shows 80.8% accuracy. In addition, when the zero-skipping scheme was employed, the energy efficiency of the proposed architecture improved from 8.13 to 58.69 TOPS/W.

• Offset-canceling current-sampling sense amplifier for resistive nonvolatile memory in 65-nm CMOS 

IEEE Journal of Solid-State Circuits (JSSC). Feb. 2017.

Resistive nonvolatile memory (NVM) is considered to be a leading candidate for next-generation memory. However, maintaining a target sensing margin is a challenge with technology scaling because of the increased process variation and decreased read cell current. This paper proposes an offset-canceling current-sampling sense amplifier (OCCS-SA) that is intended for use in deep submicrometer resistive NVM. The proposed OCCS-SA has the three major advantages of 1) offset voltage cancellation, 2) double sensing margin structure, and 3) strong positive feedback. The measurement results from a 65-nm test chip show that the proposed OCCS-SA achieves 2.4 times faster sensing time (tSEN) at a nominal supply voltage (VDD) of 1.0 V and a greater than 20% reduction in VDD at the same tSEN, compared to the state-of-the-art current-sampling-based SA, which features offset voltage cancellation and weak positive feedback. 

보유 장비

• 칩 설계 및 시뮬레이션용 Server 5대 (SVC: 20Core, SVC2: 36Core, SVC3: 10Core, SVC6: 40Core, SVC8: 40Core, SVC9: 48Core)

• 인공지능/딥러닝 시스템 시뮬레이션용 GPU Server 3대 (SVC4: 3GPU+16Core, SVC5: 2GPU+12Core, SVC7: 2GPU+12Core)

• Oscilloscope (BW=1GHz) 2대

• 이 외의 각종 테스트 장비 보유