Research

Research Area

• High speed and low power semiconductor circuit design for random computations

• PVT variation tolerant and low power circuit design for Memory & MCU (memory read/write circuit, F/F, logic, ALU, CAM, normally-off computing) 

• High security level circuit design for MCU (RNG, PUF) 

• Deep learning neuromorphic SoC, in-memory computing (IMC), compute-in-memory (CIM), PIM, etc.

Research Highlight

• A practical MRAM logic-in-memory platform with reference-bitline structure

IEEE Solid-State Circuits Letters (SSC-L). Sep. 2026.

The memory wall due to data movement is a major challenge that limits performance and energy efficiency in bitwise-operation-intensive applications. To address this issue, this paper proposes a global merged reference-based magnetic random-access memory (MRAM) logic-in-memory structure. The proposed structure generates operation-specific reference resistances by controlling the effective parallelism of the reference bitlines (Ref-BLs) while maintaining the initial reference-cell configuration, thereby supporting memory read and two-input AND/OR operations without rewriting the reference cells or using dedicated AND/OR logic blocks. A read-disturbance-free scheme is also applied to protect the frequently accessed reference cells. A 32-kb test chip fabricated in a 28-nm FD-SOI process achieved sensing yields of 100%, 98.63%, and 99.73% and normalized energies per bit of 0.97×, 0.54×, and 0.49× relative to conventional MRAM for memory read, OR, and AND operations, respectively. Full-system evaluations achieved speedups of 2.23×–2.50× and 3.14×–4.97×, with normalized dynamic energy consumption of 0.39×–0.44× and 0.23×–0.30×, for bitmap-index queries and bitmap-based breadth-first search, respectively.

• Reliability-enhanced offset-canceling current-sampling sense amplifier for 2T-2MTJ MRAM PUF

IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I). Mar. 2026. (Link)

In this paper, we propose a reliability-enhanced offset-canceling current sampling sense amplifier (REOCCS-SA) with a clamp voltage trimming technique to improve uniformity and uniqueness in spin-transfer-torque magnetic random-access memory (STT-MRAM)-based physically unclonable function (PUF). REOCCS-SA retains the structure of the OCCS-SA while incorporating a preliminary voltage amplification phase to enhance offset tolerance, thereby improving uniformity and uniqueness. Additionally, the clamp voltage trimming technique utilizes a resistor ladder to precisely adjust the clamp voltage, optimizing the reference current to achieve ideal uniformity. HSPICE simulations based on a 28 nm technology model show that the proposed REOCCS-SA reduces the standard deviation of uniformity by 75% and improves inter-Hamming distance (inter-HD) by 50% compared to the OCCS-SA. In addition, compared to other circuits proposed within the past decade, it achieves the lowest figure of merit, demonstrating the highest overall efficiency when operating as an STT-MRAM-based PUF. Furthermore, by applying the VCMP_R trimming and the automatic write-back technique, the PUF system using REOCCS-SA exhibits 49.95% uniformity, 50.83% inter-HD, and 0% intra-Hamming distance, confirming its overall robustness and stability.

• Ternary output binary neural network with zero-skipping for MRAM-based digital in-memory computing

IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II). Jul. 2023. (Link)

This paper presents a novel ternary output binary neural network (BNN) and an MRAM-based digital in-memory computing (IMC) architecture. The proposed ternary output BNN and IMC architecture is capable of 1) improving array efficiency by using only one bit-cell for one synaptic weight, 2) no accuracy loss due to its digital nature, 3) high energy efficiency by employing a zero-skipping scheme, and 4) the use of normal memory and deep learning applications due to minimized array modification. System simulations with a two-layer perceptron show that the ternary output BNN achieves 92.12% inference accuracy measured against the MNIST dataset, while the conventional BNN shows 80.8% accuracy. In addition, when the zero-skipping scheme was employed, the energy efficiency of the proposed architecture improved from 8.13 to 58.69 TOPS/W.

• Offset-canceling current-sampling sense amplifier for resistive nonvolatile memory in 65-nm CMOS 

IEEE Journal of Solid-State Circuits (JSSC). Feb. 2017. (Link)

Resistive nonvolatile memory (NVM) is considered to be a leading candidate for next-generation memory. However, maintaining a target sensing margin is a challenge with technology scaling because of the increased process variation and decreased read cell current. This paper proposes an offset-canceling current-sampling sense amplifier (OCCS-SA) that is intended for use in deep submicrometer resistive NVM. The proposed OCCS-SA has the three major advantages of 1) offset voltage cancellation, 2) double sensing margin structure, and 3) strong positive feedback. The measurement results from a 65-nm test chip show that the proposed OCCS-SA achieves 2.4 times faster sensing time (tSEN) at a nominal supply voltage (VDD) of 1.0 V and a greater than 20% reduction in VDD at the same tSEN, compared to the state-of-the-art current-sampling-based SA, which features offset voltage cancellation and weak positive feedback. 

보유 장비

• 칩 설계 및 시뮬레이션용 Server 6대 (SVC: 20Core, SVC2: 36Core, SVC3: 10Core, SVC6: 40Core, SVC8: 40Core, SVC9: 48Core)

• 인공지능/딥러닝 시스템 시뮬레이션용 GPU Server 3대 (SVC4: 3GPU+16Core, SVC5: 2GPU+12Core, SVC7: 2GPU+12Core)

• Oscilloscope (BW=1GHz) 2대

• 이 외의 각종 테스트 장비 (FPGA, Signal Generator, Power Supply, Multimeter 등) 보유