Conference

International Conference Papers 

(† Equally Credited Authors, * Corresponding Authors) 

  [2024]

[12] M. Han, S. Yang, and T. Na*, “Low power offset-tolerant sense amplifier using dynamic boosting,” in IEEE/IEIE International Conference on Consumer Electronics-Asia (ICCE-Asia), Danang, Vietnam, Nov. 2024. (submitted)


  [2023]

[11] S. Ahn, J. Lee, and T. Na*, “Tiny machine learning hardware implementation of handwritten digit inference using arduino and ternary output binary neural network,” in IEEE/IEIE International Conference on Consumer Electronics-Asia (ICCE-Asia), Busan, Republic of Korea, Oct. 2023. (Link)


  [2021]

[10] T. Na*, “Offset voltage analysis and enable signal rise time control based offset reduction technique of current-latched sense amplifier,” in IEIE/IEEE Int. Conf. Electronics, Information, and Communication (ICEIC), Jeju, Republic of Korea, Jan. 2021. (Link)


  [2020]

[9] T. Na, S. H. Kang, and S.-O. Jung*, “Tail fitting yield estimation method for resistive non-volatile memory,” in IEIE/IEEE Int. Conf. Electronics, Information, and Communication (ICEIC), Barcelona, Spain, Jan. 2020. (Link)


  [2016]

[8] B. Yoo, T. Na, B. Song, S. H. Kang, J. P. Kim, and S.-O. Jung*, “Equalization scheme analysis for high-density spin transfer torque random access memory,” in Int. SoC Design Conf. (ISOCC), Oct. 2016, pp. 100-101. (Link) 

[7] S. Choi, T. Na, S. H. Kang, J. P. Kim, and S.-O. Jung*, “Area-optimal sensing circuit designs in deep submicrometer STT-RAM,” in IEEE Int. Symp. Circuits and Systems (ISCAS), May 2016, pp. 1246-1249. (Link) 


  [2015]

[6] T. Na, H. Jeong, J. P. Kim, S. H. Kang, and S.-O. Jung*, “Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter,” in IEEE Int. Conf. Electronics, Circuits, and Systems (ICECS), Cairo, Egypt, Dec. 2015, pp. 400-403. (Link) 

[5] B. Song, T. Na, S. H. Kang, J. P. Kim, and S.-O. Jung*, “Reference-circuit analysis for high-bandwidth spin transfer torque random access memory,” in ACM/IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Jul. 2015, pp. 365-370. (Link) 


  [2014]

[4] B. Song, T. Na, J. Kim, H. Jeong, S. H. Kang, J. P. Kim, and S.-O. Jung*, “Comparative analysis of using planar MOSFET and FinFET as access transistor of STT-RAM cell in 22-nm technology node,” in Int. SoC Design Conf. (ISOCC), Nov. 2014, pp. 112-113. (Link) 

[3] T. Na, K. Ryu, J. Kim, J. P. Kim, S. H. Kang, and S.-O. Jung*, “High-performance low-power magnetic tunnel junction based non-volatile flip-flop,” in IEEE Int. Symp. Circuits and Systems (ISCAS), Melbourne, Australia, Jun. 2014, pp. 1953-1956. (Link)


  [2013]

[2] B. Song, T. Na, J. Kim, S. H. Kim, J. P. Kim, and S.-O. Jung*, “Sensing circuit optimization using different type of transistors for deep submicron STT-RAM,” in Int. SoC Design Conf. (ISOCC), Nov. 2013, pp. 68-71. (Link) 

[1] T. Na, K. Ryu, J. Kim, S. H. Kang, and S.-O. Jung*, “A comparative study of STT-MTJ based non-volatile flip-flops,” in IEEE Int. Symp. Circuits and Systems (ISCAS), Beijing, China, May 2013, pp. 109-112. (Link) 

Domestic Conference Papers 

(† Equally Credited Authors, * Corresponding Authors) 

[9] 김재환, 나태희*, "상승 시간 제어 기술을 사용한 바디 바이어스 전압 래치 감지 증폭기," in 대한전자공학회 하계종합학술대회, Jun. 2024.

[8] 지창훈, 나태희*, "프리차지2 스위치 및 더미 캡이 있는 전류 랫치 센스 엠프," in 대한전자공학회 하계종합학술대회, Jun. 2024.

[7] 안성민, 나태희*, "MLC-MRAM 기반 디지털 PIM의 이점과 Sensing Margin 분석," in 대한전자공학회 추계학술대회, Nov. 2023. (Link)

[6] 바야르툴가, 나태희*, "Sub-threshold 전압 영역 Magnetic-tunnel-junction 기반 Body-biasing을 이용한 비휘발성 Flip-Flop," in 대한전자공학회 하계종합학술대회, Jun. 2021. (Link)

[5] 오대성, 나태희*, "STT-MRAM의 Near/Far Cell에 대한 Read Operation과 Yield 분석," in 대한전자공학회 하계종합학술대회, Jun. 2021. (Link)

[4] 김도연, 나태희*, "Sense Enable Rise Time을 이용한 Current-Latched Sense Amplifier의 Offset Voltage 감소 기법 분석," in 대한전자공학회 하계종합학술대회, Jun. 2021. (Link)

[3] 김성훈, 나태희*, "비휘발성 메모리에서 공급 전압에 따른 Source Degeneration의 효과," in 대한전자공학회 하계종합학술대회, Jun. 2021. (Link)

[2] 최광휘, 나태희*, "Restore Yield와 Read Disturbance를 고려한 STT-MTJ 기반 저전력 비휘발성 Flip-Flop 분석," in 대한전자공학회 하계종합학술대회, Aug. 2020. (Link)

[1] 최사라, 나태희, 송병규, 김정필, 강승혁, 정성욱*, “차세대 메모리를 위한 병렬적 Double Error Correcting BCH 복호기 설계에 관한 연구,” in 대한전자공학회 하계종합학술대회, Jun. 2015, pp. 129-132. (Link)