Journal

International Journal Papers 

  [2024]

[32] J. Kim and T. Na*, “Body-biased voltage-latched sense amplifier with rise-time control technique for SRAM,” Submitted.

[31] D. Ahn, S. Ahn, and T. Na*, “Area-optimized and reliable computing-in-memory platform based on STT-MRAM,” Under revision.

[30] J. Yu, G. Lee, and T. Na*, “High-performance sum operation with charge saving and sharing circuit for MRAM-based in-memory computing,” IEIE J. Semicond. Technol. Sci. (JSTS), vol. 22, no. 2, pp. 111-121, Apr. 2024. (SCIE)  (Link)

  [2023]

[29] B. Ishdorj and T. Na*, “Spin-transfer-torque magnetic-tunnel-junction-based low-power nonvolatile flip-flop designs in the subthreshold voltage region,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 31, no. 10, pp. 1565-1577, Oct. 2023. (SCIE) (Link)

[28] B. Ishdorj†, D. Kim†, S. Ahn, and T. Na*, “Offset-canceling current-latched sense amplifier with slow rise time control and reference voltage biasing techniques,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 70, no. 7, pp. 2689-2699, Jul. 2023. (SCIE) (Link)

[27] T. Na*, “Ternary output binary neural network with zero-skipping for MRAM-based digital in-memory computing,” IEEE Trans. Circuits Syst. II, Exp. Briefs (TCAS-II), vol. 70, no. 7, pp. 2655-2659, Jul. 2023. (SCIE) (Link)

  [2022]

[26] B. Ishdorj†, Jeongyeon Kim†, Jaehwan Kim, and T. Na*, “A timing-based split-path sensing circuit for STT-MRAM,” MDPI Micromachines, vol. 13, no. 7, p. 1004, Jun. 2022. (SCIE) (Link)

[25] N. Kumar, D. Mishra, S. G. Seo, T. Na*, and S. H. Jin*, “Hierarchical formation of Ni sulfide single walled carbon nanotubes heterostructure on tin-sulfide scaffolds via mediated SILAR process: application towards long cycle-life solid-state supercapacitors,” Elsevier Ceramics International, vol. 48, no. 12, pp. 16656-16666, Jun. 2022. (SCIE) (Link)

   [2021]

[24] T. Na*, “Study on cross-coupled-based sensing circuits for nonvolatile flip-flops operating in near/subthreshold voltage region,” MDPI Micromachines, vol. 12, no. 10, p. 1177, Oct. 2021. (SCIE)  (Link)

[23] T. Na*, “Body-biasing-based latch offset cancellation sensing circuit for deep submicrometer STT-MRAM,” IEIE J. Semicond. Technol. Sci. (JSTS), vol. 21, no. 2, pp. 126-133, Apr. 2021. (SCIE)  (Link)

[22] T. Na*, S. H. Kang, and S.-O. Jung, “STT-MRAM sensing: a review,” IEEE Trans. Circuits Syst. II, Exp. Briefs (TCAS-II), vol. 68, no. 1, pp. 12-18, Jan. 2021. (SCIE) (Link)

   [2020]

[21] G. H. Choi and T. Na*, “Analysis of state-of-the-art spin-transfer-torque nonvolatile flip-flops considering restore yield in the near/sub-threshold voltage region,” MDPI Electronics, vol. 9, no. 12, p. 2118, Dec. 2020. (SCIE) (Link)

[20] N. Kumar, D. Mishra, S. Y. Kim, T. Na*, and S. H. Jin*, “Two dimensional, sponge-like In2S3 nanoflakes aligned on nickel foam via one-pot solvothermal growth and their application toward high performance supercapacitors,” Elsevier Materials Letters, vol. 279, p. 128467, Nov. 2020. (SCIE) (Link)

[19] G. H. Choi and T. Na*, “Novel MTJ-based sensing inverter variation tolerant nonvolatile flip-flop in the near-threshold voltage region,” IEEE Access, vol. 8, pp. 191057-191066, Oct. 2020. (SCIE) (Link)

[18] N. Kumar, D. Mishra, S. Y. Kim, T. Na*, and S. H. Jin*, “Directly grown two dimensional In2S3 nanoflakes via one-step solvothermal method: material properties on In2S3 and performance data for supercapacitors,” Elsevier Data in Brief, vol. 32, p. 106272, Oct. 2020. (ESCI) (Link)

[17] T. Na*, “Robust offset-cancellation sensing-circuit-based spin-transfer-torque nonvolatile flip-flop,” IEEE Access, vol. 8, pp. 159806-159815, Sep. 2020. (SCIE) (Link)

[16] T. Na*, “Robust offset-cancellation sense amplifier for an offset-canceling dual-stage sensing circuit in resistive nonvolatile memories,” MDPI Electronics, vol. 9, no. 9, p. 1403, Sep. 2020. (SCIE) (Link)

[15] T. Na*, S. H. Kang, and S.-O. Jung, “Distribution analysis and multiple-point tail fitting yield estimation method for STT-MRAM,” IEIE J. Semicond. Technol. Sci. (JSTS), vol. 20, no. 3, pp. 271-280, Jun. 2020. (SCIE) (Link)

   [2019]

[14] T. Na, B. Song, S. Choi, J. P. Kim, S. H. Kang, and S.-O. Jung*, “Offset-canceling single-ended sensing scheme with one-bit-line precharge architecture for resistive non-volatile memory in 65 nm CMOS,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 27, no. 11, pp. 2548-2555, Nov. 2019. (SCIE) (Link)

   [2018]

[13] T. Na, B. Song, J. P. Kim, S. H. Kang, and S.-O. Jung*, “Data-cell-variation-tolerant dual-mode sensing scheme for deep submicrometer STT-RAM,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 65, no. 1, pp. 163-174, Jan. 2018. (SCIE) (Link)

   [2017]

[12] B. Song, T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung*, “A 10T-4MTJ nonvolatile ternary CAM cell for reliable search operation and compact area,” IEEE Trans. Circuits Syst. II, Exp. Briefs (TCAS-II), vol. 64, no. 6, pp. 700-704, Jun. 2017. (SCIE) (Link)

[11] T. Na, B. Song, J. P. Kim, S. H. Kang, and S.-O. Jung*, “Offset-canceling current-sampling sense amplifier for resistive nonvolatile memory in 65-nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 52, no. 2, pp. 496-504, Feb. 2017. (SCIE) (Link)

   [2016]

[10] T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung*, “Multiple-cell reference scheme for reduced reference resistance distribution in deep submicrometer STT-RAM,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 24, no. 9, pp. 2993-2997, Sep. 2016. (SCIE) (Link)

[9] S. Choi, T. Na, J. Kim, J. P. Kim, S. H. Kang, and S.-O. Jung*, “Corner-aware dynamic gate voltage scheme to achieve high read yield in STT-RAM,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 24, no. 9, pp. 2851-2860, Sep. 2016. (SCIE) (Link)

[8] T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung*, “Read disturbance reduction technique for offset-canceling dual-stage sensing circuits in deep submicrometer STT-RAM,” IEEE Trans. Circuits Syst. II, Exp. Briefs (TCAS-II), vol. 63, no. 6, pp. 578-582, Jun. 2016. (SCIE) (Link)

[7] T. Na, J. Kim, B. Song, J. P. Kim, S. H. Kang, and S.-O. Jung*, “An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 24, no. 4, pp. 1361-1370, Apr. 2016. (SCIE) (Link)

   [2015]

[6] T. Na, J. Kim, J. P. Kim, S. H. Kang, and S.-O. Jung*, “A double-sensing-margin offset-canceling dual-stage sensing circuit for resistive nonvolatile memory,” IEEE Trans. Circuits Syst. II, Exp. Briefs (TCAS-II), vol. 62, no. 12, pp. 1109-1113, Dec. 2015. (SCIE) (Link) 

[5] B. Song, T. Na, J. Kim, J. P. Kim, S. H. Kang, and S.-O. Jung*, “Latch offset cancellation sense amplifier for deep submicrometer STT-RAM,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 62, no. 7, pp. 1776-1784, Jul. 2015. (SCIE) (Link)

    [2014]

[4] T. Na, J. Kim, J. P. Kim, S. H. Kang, and S.-O. Jung*, “Reference-scheme study and novel reference scheme for deep submicrometer STT-RAM,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 61, no. 12, pp. 3376-3385, Dec. 2014. (SCIE) (Link)

[3] T. Na, J. Kim, J. P. Kim, S. H. Kang, and S.-O. Jung*, “An offset-canceling triple-stage sensing circuit for deep submicrometer STT-RAM,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 22, no. 7, pp. 1620-1624, Jul. 2014. (SCIE) (Link)

[2] J. Kim, T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung*, “A split-path sensing circuit for spin torque transfer MRAM (STT-MRAM),” IEEE Trans. Circuits Syst. II, Exp. Briefs (TCAS-II), vol. 61, no. 3, pp. 193-197, Mar. 2014. (SCIE) (Link)

[1] T. Na, S.-H. Woo, J. Kim, H. Jeong, and S.-O. Jung*, “Comparative study of various latch-type sense amplifiers,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 22, no. 2, pp. 425-429, Feb. 2014. (SCIE) (Link)

Domestic Journal Papers

[1]