S. Lee, D. Ahn, S. H. Jin*, and T. Na*, “Digital-memory hybrid counter-based SRAM in-memory computing,” submitted to JSTS. (under revision, major).
D. Ahn†, S. Ahn†, S. Lee, and T. Na*, “Area-efficient/low-power MRAM-PIM based on crossbar array utilizing ternary output,” IEEE Trans. Magn. (TMAG), accepted. (SCIE) (Link)
안다솜, 이시열, 나태희*, “STT-MRAM 기반 베이지안 신경망 구현에 대한 통합적 분석,” 전자공학회논문지, vol. 62, no. 12, pp. xx-yy, Dec. 2025. accepted. (KCI)
D. Ahn, S. Ahn, S. Lee, and T. Na*, “Area-efficient/low-power MRAM-PIM based on crossbar array utilizing ternary output,” in Int. SoC Design Conf. (ISOCC), Busan, Republic of Korea, Oct. 2025. (Not Published on IEEE Xplore)
S. Lee, G. Lee, S. Ahn, and T. Na*, “Analysis of low area digital up/down clipping counter for digital in-memory computing,” IEEE Access, vol. 13, pp. 32808-32818, Jan. 2025. (SCIE) (Link)