D. Ahn†, S. Ahn†, S. Lee, and T. Na*, “Area-efficient/low-power MRAM-PIM based on crossbar array utilizing ternary output,” submitted to TMAG. (under revision, major).
S. Ahn and T. Na*, “Single-reference-based multi-level cell sensing scheme for spin-orbit torque MRAM,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 72, no. 10, pp. 5785-5796, Oct. 2025. (SCIE) (Link)
D. Ahn, S. Ahn, and T. Na*, “Area-optimized and reliable computing-in-memory platform based on STT-MRAM,” IEIE J. Semicond. Technol. Sci. (JSTS), vol. 25, no. 1, pp. 56-65, Feb. 2025. (SCIE) (Link)
S. Lee, G. Lee, S. Ahn, and T. Na*, “Analysis of low area digital up/down clipping counter for digital in-memory computing,” IEEE Access, vol. 13, pp. 32808-32818, Jan. 2025. (SCIE) (Link)
나태희, 안성민, "10-2024-0139601: 자기 랜덤 액세스 메모리를 위한 컴퓨팅 인 메모리 동작 제어 방법 및 자기 랜덤 액세스 메모리," Oct. 14. 2024. (국내 특허 출원)
안성민, 나태희*, "MLC-MRAM 기반 디지털 PIM의 이점과 Sensing Margin 분석," in 대한전자공학회 추계학술대회, Nov. 2023. (Link)
S. Ahn, J. Lee, and T. Na*, “Tiny machine learning hardware implementation of handwritten digit inference using arduino and ternary output binary neural network,” in IEEE/IEIE International Conference on Consumer Electronics-Asia (ICCE-Asia), Busan, Republic of Korea, Oct. 2023. (Link)
B. Ishdorj†, D. Kim†, S. Ahn, and T. Na*, “Offset-canceling current-latched sense amplifier with slow rise time control and reference voltage biasing techniques,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 70, no. 7, pp. 2689-2699, Jul. 2023. (SCIE) (Link)