Jaeyong Jang (장재용)

Publication († Equally Credited Authors, * Corresponding Authors) 

1. J. Jang, M. Han, and T. Na*, “OCDC for MRAM,” in preparation.

2. J. Jang, C. Lee, C. Ji, and T. Na*, “FPGA-based RNG and its applications,” in preparation.

3. J. Jang†, B. Ishdorj†, U. Saha, and T. Na*, “Recovery-signal-based low-cost quadruple-node-upset-tolerant and self-recoverable latch design for aerospace applications,” submitted to TAES. (under revision, minor).

4. M. Han, J. Kim, B. Ishdorj, J. Jang, and T. Na*, “Reliability-enhanced offset-canceling current-sampling sense amplifier for 2T-2MTJ MRAM PUF,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), accepted. (SCIE) (Link)

5. 나태희, 한민구, 장재용, "10-2025-0193620: 자기 랜덤 액세스 메모리용 오프셋 제거 방전 기반 싱글 엔디드 감지기 및 그 제어 방법," Dec. 9. 2025. (국내 특허 출원) 

6. U. Saha†, B. Ishdorj†, J. Jang, and T. Na*, “Double-node-upset fully-tolerant/recoverable and triple-node-upset partially-tolerant self-recoverable latch design for aerospace applications,” IEEE Access, vol. 13, pp. 193098-193112, Nov. 2025. (SCIE) (Link)