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Semiconductor
Electronic Design Automation (EDA) Tool Development
As device technology research takes years and is very expensive, it is desirable to evaluate a technology’s potential as early as possible. Nonetheless, conventional models do not fully consider the distinctive properties of emerging materials such as organic, oxide, two-dimensional, carbon-based semiconductors and the devices made of such materials. Our group study the charge injection and transport mechanism to envisage a new device model that enables simple, accurate and rigorous description of device behavior. Furthermore, we translate our findings into a compact model for SPICE simulation to conduct design technology co-optimization (DTCO) at a circuit level including parasitic effects.
#CompactModel #SPICE #TCAD #DTCO
AI-Optimized Digital Twin for Semiconductor Manufacturing
Semiconductor manufacturing is getting more complex and expensive. In addition, running DoE with wafers to optimize fabs is not scaling. Furthermore, no two fab lines are identical. Thereby, traditional methods of optimizing fab processes is slow. By using AI and digital twin, we envisage semiconductor manufacturing cost and time-to-yield reduction.
Memristor Devices and Crossbar Array (CBA) for AI Accelerator
AI accelerator is gaining in importance as the demand for AI increases in various domains of applications, such as natural language processing, computer vision, etc. The state-of-the-art approach of building a multiplication and accumulation (MAC) based on digital logic gates is not free from a significant power comsumption and delay due to the von Neumann architecture. A cross bar array (CBA) of memristor devices (i.e. resistive switching memory) is analogous to an artificial neural network that processes the MAC operation, which makes it a promising candidate for the next generation AI accelerator. Our group collaborate with KIST, KAIST, Catholic University of Korea and Alsemy to build a multi-scale simulation platform to predict and analyze the behavior of CBA. In doing so, we conduct a convergence research of data science, computer science, device physics and electrical engineering to introduce artificial intelligence (AI) in electronic design automation.
#Memristor #CrossbarArray #MAC #AIAccelerator
Post-CMOS Logic Devices
Along the aggressive progress of semiconductor technology, device engineering has been pushed to an extreme situation to mitigate severe power consumption and heavy integration density. A reconfigurable field-effect transistors (RFET) is a low-power dynamically programmable logic device. The polarity of an RFET can be switched between n-type and p-type by the voltage applied to a polarity gate. This functional extension could unleash the Moore's law set by a type-fixed device, i.e. Metal-Oxide-Semiconductor FET (MOSFET), and Complementary Metal-Oxide Semiconductor (CMOS) technology. Our group collaborate with the Electronics and Telecommunications Research Institute (ETRI) to address fabrication and design issues ahead of technical development of the new kid on the block.
#CMOS #LogicDevice #ReconfigurableFET
Semiconductor & Device Physics
Charge transport in amorphous semiconductors manifests through the thermally-assisted hopping transport. This behavior is extremely different to that we find in crystalline semiconductors where charge transport occurs by the band transport. Our group gains fundamental insights on the hopping transport mechanism considering both energetic and spatial disorder from kinetic-Monte-Carlo (k-MC) simulation, and formulate a physical master equation for Technology Computer-Aided Design (TCAD) tool.
#ChargeTransport #PhysicalModeling #AmorphousSemiconductor
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