SS Cheema, JH Bae, S Salahuddin, et al., Nature, 604, 65-71 (2022)
https://doi.org/10.1038/s41586-022-04425-6
Negative Capacitance FET (Fabrication, Design, Modeling)
Nanoscale MOSFET (Design, Analysis/Modeling - Foundry Tech. Level)
Semiconductor Device Modeling
Circuit Design & Fabrication (SNU-ISRC, ETRI, NNFC, IDEC, ...)
MK Park, JH Bae, et al., IEEE TED, 69(2), 832-837 (2021)
JH Bae, JH Lee et al., IEEE EDL, 40(4), 624-627 (2019)
Charge Trap Memory with 'New' Design
- Reconfigurable FET (CTF - Gate Array)
- Gated Schottky Diode & Gated Diode (Barristor)
Ferroelectric Memory - Embedded Memory, NOR/NAND Array
Capacitorless DRAM - 2T0C, 1T0C DRAM
Vertically Stacked Memory (AND/NAND Array) Design & Fabrication
Operating Mechanism Analysis & Modeling
JH Bae, D Kwon, et al., IEEE EDL, 43(6), 958-961 (2022)
JH Bae, D Kwon, et al., IEEE EDL, 41(8), 1201-1204 (2020)
Low-Frequency Noise (LFN)
- Conduction Mechanism Analysis
- Defect / Electrical Response Analysis
Transient Response Analysis
- Defect/Device Operation Speed Analysis
- Transient Response Spectroscopy - Characteristic Time of Defects
TCAD Simulation-Based Device Modeling & Analysis
- Device Structure Optimization
- New Device Design, Circuit Analysis - Mixed-Mode Simulation
MK Park, JH Bae, JH Lee et al., IEEE TED, 70(1), 93-98 (2023)
SY Woo, JH Bae, et al., IEEE EDL, 44(1), 5-8 (2023)
Function Device/Memory Element Development (PF Device, Latch-up Device, Transistor-Based Sensors, etc.)
Adaptation of a New Device into IC (CMOS Fabrication Compatible Device Design)
Simplification of a Complex Circuit Using New Concept Devices
D Kwon, JH Bae, JH Lee et al., (Submitted)
Memory Array Fabrication
Device Variation/Reliability Analysis
PIM Architecture Design
Neural Network Simulation & Hardware Evaluation