Publications
Conference Papers
Conference Papers
[22] Q. Zhang*, Shiyu Su*, Z. Liu*, H.-C. Cheng, Z. Qiu., M. Palaria, J. Ye, D. Meng, B. Chen, S. Hossain, W. Wu, and Mike Chen, “A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems,” in IEEE Symp. on VLSI Circuits, Jun. 2024. (* equal contribution)
[22] Q. Zhang*, Shiyu Su*, Z. Liu*, H.-C. Cheng, Z. Qiu., M. Palaria, J. Ye, D. Meng, B. Chen, S. Hossain, W. Wu, and Mike Chen, “A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems,” in IEEE Symp. on VLSI Circuits, Jun. 2024. (* equal contribution)
[21] Q. Zhang*, Shiyu Su*, B. R. Biswas, S. Gupta, and Mike Chen, “Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder With 0.012mm2 Active Area in 12nm FinFET,” in IEEE Symp. on VLSI Circuits, Jun. 2024. (* equal contribution)
[21] Q. Zhang*, Shiyu Su*, B. R. Biswas, S. Gupta, and Mike Chen, “Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder With 0.012mm2 Active Area in 12nm FinFET,” in IEEE Symp. on VLSI Circuits, Jun. 2024. (* equal contribution)
[20] M. Palaria, Shiyu Su, H.-C. Cheng, R. Rasul, Q. Zhang, S. Mahapatra, C.-F. Law, S. Hossain, R. Bena, W. Wu, Q. Nguyen, M. S.-W. Chen, "Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS", in IEEE European Solid State Circuits Conference (ESSCIRC), Sep. 2023.
[20] M. Palaria, Shiyu Su, H.-C. Cheng, R. Rasul, Q. Zhang, S. Mahapatra, C.-F. Law, S. Hossain, R. Bena, W. Wu, Q. Nguyen, M. S.-W. Chen, "Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS", in IEEE European Solid State Circuits Conference (ESSCIRC), Sep. 2023.
[19] H.-C. Cheng, Shiyu Su, M. Palaria, Q. Zhang, C. Yang, S. Hossain, R. Bena, B. Chen, Z. Liu, J. Liu, R. Rasul, Q. Nguyen, W. Wu, M. S.-W. Chen, "A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems," in IEEE Custom Integrated Circuits Conference (CICC), April 2023.
[19] H.-C. Cheng, Shiyu Su, M. Palaria, Q. Zhang, C. Yang, S. Hossain, R. Bena, B. Chen, Z. Liu, J. Liu, R. Rasul, Q. Nguyen, W. Wu, M. S.-W. Chen, "A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems," in IEEE Custom Integrated Circuits Conference (CICC), April 2023.
[18] Shiyu Su*, Qiaochu Zhang*, and M. S.-W. Chen, “A 2GS/s 8.5-Bit Time-Based ADC Using a Segmented Stochastic Flash TDC,” in IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023 (* equal contribution)
[18] Shiyu Su*, Qiaochu Zhang*, and M. S.-W. Chen, “A 2GS/s 8.5-Bit Time-Based ADC Using a Segmented Stochastic Flash TDC,” in IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023 (* equal contribution)
[17] Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su and Mike Chen, “A Fractional-N Digital MDLL with Injection Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023.
[17] Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su and Mike Chen, “A Fractional-N Digital MDLL with Injection Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023.
[16] Ce Yang, Shiyu Su and Mike Chen, “A Millimeter-Wave Mixer-First Receiver with Non-Uniform Time-Approximation Filter Achieving >45-dB Blocker Rejection,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2022. (Best Student Paper Award - First Place)
[16] Ce Yang, Shiyu Su and Mike Chen, “A Millimeter-Wave Mixer-First Receiver with Non-Uniform Time-Approximation Filter Achieving >45-dB Blocker Rejection,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2022. (Best Student Paper Award - First Place)
[15] Qiaochu Zhang*, Shiyu Su* and Mike Chen, "A Cost-Efficient Fully Synthesizable Stochastic Time-to-Digital Converter Design Based on Integral Nonlinearity Scrambling," in 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC), July 2022. (* equal contribution)
[15] Qiaochu Zhang*, Shiyu Su* and Mike Chen, "A Cost-Efficient Fully Synthesizable Stochastic Time-to-Digital Converter Design Based on Integral Nonlinearity Scrambling," in 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC), July 2022. (* equal contribution)
[14] Shiyu Su and Mike Chen, “High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2022. (Best Invited Paper Candidate)
[14] Shiyu Su and Mike Chen, “High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2022. (Best Invited Paper Candidate)
[13] Shiyu Su Q. Zhang, M. Hassanpourghadi, J. Liu, R.A. Rasul,and Mike Chen, “AMS Circuit Synthesis Enabled by the Advancements of Circuit Architectures and ML Algorithms,” in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2022. (Invited)
[13] Shiyu Su Q. Zhang, M. Hassanpourghadi, J. Liu, R.A. Rasul,and Mike Chen, “AMS Circuit Synthesis Enabled by the Advancements of Circuit Architectures and ML Algorithms,” in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2022. (Invited)
[12] Shiyu Su, Q. Zhang, J. Liu, M. Hassanpourghadi, R.A. Rasul, and Mike Chen, “TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture,” in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2022.
[12] Shiyu Su, Q. Zhang, J. Liu, M. Hassanpourghadi, R.A. Rasul, and Mike Chen, “TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture,” in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2022.
[11] J. Liu, Shiyu Su, M. Madhusudan, M. Hassanpourghadi, S. Saunders, Q. Zhang, R. Rasul, Y. Li, J. Hu, A. K. Sharma, S. S. Sapatnekar, R. Harjani, A. Levi, S. Gupta and Mike Chen “From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning,” in 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2021.
[11] J. Liu, Shiyu Su, M. Madhusudan, M. Hassanpourghadi, S. Saunders, Q. Zhang, R. Rasul, Y. Li, J. Hu, A. K. Sharma, S. S. Sapatnekar, R. Harjani, A. Levi, S. Gupta and Mike Chen “From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning,” in 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2021.
[10] M. Hassanpourghadi, Shiyu Su, R.A. Rasul, J. Liu, Q. Zhang, and Mike Chen, “Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling,” in 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC), Dec. 2021.
[10] M. Hassanpourghadi, Shiyu Su, R.A. Rasul, J. Liu, Q. Zhang, and Mike Chen, “Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling,” in 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC), Dec. 2021.
[9] Q. Zhang, Shiyu Su, C.-R. Ho, and Mike Chen, “A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (Invited for demo)
[9] Q. Zhang, Shiyu Su, C.-R. Ho, and Mike Chen, “A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (Invited for demo)
[8] Q. Zhang, Shiyu Su, J. Liu and Mike Chen, “CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation,” in 2020 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2020.
[8] Q. Zhang, Shiyu Su, J. Liu and Mike Chen, “CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation,” in 2020 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2020.
[7] J. Liu, M. Hassanpourghadi, Q. Zhang, Shiyu Su and Mike Chen, “Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling,” in 2020 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2020.
[7] J. Liu, M. Hassanpourghadi, Q. Zhang, Shiyu Su and Mike Chen, “Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling,” in 2020 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2020.
[6] Shiyu Su and Mike Chen, “A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation,” in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb. 2020.
[6] Shiyu Su and Mike Chen, “A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation,” in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb. 2020.
[5] Shiyu Su and Mike Chen, “A 1–5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM,” in IEEE Symp. on VLSI Circuits Dig. Tech. Papers, C20-C21, Jun. 2019.
[5] Shiyu Su and Mike Chen, “A 1–5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM,” in IEEE Symp. on VLSI Circuits Dig. Tech. Papers, C20-C21, Jun. 2019.
[4] M. Hassanpourghadi, Q. Zhang, P. Sharma, J. Nam, Shiyu Su, S. Chowdhury, J. Sathyamoorthy, W. Unglaub, F. Wang, Mike Chen, Sandeep Gupta, Anthony Levi, W. Hansford and W. Taylor, “Automated Analog Mixed Signal IP Generator for CMOS Technologies,” GOMACTech '19, March, 2019.
[4] M. Hassanpourghadi, Q. Zhang, P. Sharma, J. Nam, Shiyu Su, S. Chowdhury, J. Sathyamoorthy, W. Unglaub, F. Wang, Mike Chen, Sandeep Gupta, Anthony Levi, W. Hansford and W. Taylor, “Automated Analog Mixed Signal IP Generator for CMOS Technologies,” GOMACTech '19, March, 2019.
[3] Shiyu Su and Mike Chen, “A 16-bit 12GS/s Single/Dual-Rate DAC with Successive Bandpass Delta-Sigma Modulator Achieving <-67dBc IM3 within DC to 6GHz Tunable Passbands,” in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb. 2018.
[3] Shiyu Su and Mike Chen, “A 16-bit 12GS/s Single/Dual-Rate DAC with Successive Bandpass Delta-Sigma Modulator Achieving <-67dBc IM3 within DC to 6GHz Tunable Passbands,” in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb. 2018.
[2] Shiyu Su and Mike Chen, “A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS,” in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 456–457, Feb. 2016.
[2] Shiyu Su and Mike Chen, “A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS,” in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 456–457, Feb. 2016.
[1] Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma and Mike Chen, “A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS,” in IEEE Symp. on VLSI Circuits Dig. Tech. Papers, pp. 1-2, Jun. 2014.
[1] Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma and Mike Chen, “A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS,” in IEEE Symp. on VLSI Circuits Dig. Tech. Papers, pp. 1-2, Jun. 2014.
Peer-Reviewed Journal Papers
Peer-Reviewed Journal Papers
[8] Q. Zhang, H.-C. Cheng, Shiyu Su, and Mike Chen, “Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration,” (Invited) IEEE J. Solid-State Circuits, 2023.
[8] Q. Zhang, H.-C. Cheng, Shiyu Su, and Mike Chen, “Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration,” (Invited) IEEE J. Solid-State Circuits, 2023.
[7] C. Yang, Shiyu Su, and Mike Chen, “Millimeter-Wave Receiver with Non-Uniform Time-Approximation Filter,” (Invited) IEEE J. Solid-State Circuits, 2023.
[7] C. Yang, Shiyu Su, and Mike Chen, “Millimeter-Wave Receiver with Non-Uniform Time-Approximation Filter,” (Invited) IEEE J. Solid-State Circuits, 2023.
[6] Shiyu Su and Mike Chen, “SAW-Less Direct RF Transmitter with Multi-Mode Noise Shaping and Tri-Level Time-Approximation Filter,” IEEE J. Solid-State Circuits, 2021.
[6] Shiyu Su and Mike Chen, “SAW-Less Direct RF Transmitter with Multi-Mode Noise Shaping and Tri-Level Time-Approximation Filter,” IEEE J. Solid-State Circuits, 2021.
[5] Q. Zhang, Shiyu Su, C.-R. Ho, and Mike Chen, “A Fractional-N Digital MDLL with Background Two-Point DTC Calibration,” (Invited) IEEE J. Solid-State Circuits, 2021.
[5] Q. Zhang, Shiyu Su, C.-R. Ho, and Mike Chen, “A Fractional-N Digital MDLL with Background Two-Point DTC Calibration,” (Invited) IEEE J. Solid-State Circuits, 2021.
[4] Shiyu Su and Mike Chen, “A Time-approximation Filter for Direct RF Transmitter,” IEEE J. Solid-State Circuits, 2021.
[4] Shiyu Su and Mike Chen, “A Time-approximation Filter for Direct RF Transmitter,” IEEE J. Solid-State Circuits, 2021.
[3] Shiyu Su and Mike Chen, “A 16-bit 12GS/s Single/Dual-Rate DAC with a Successive Bandpass Delta-Sigma Modulator Achieving <-67dBc IM3 within DC to 6GHz Tunable Passbands,” (Invited) IEEE J. Solid-State Circuits, Dec. 2018.
[3] Shiyu Su and Mike Chen, “A 16-bit 12GS/s Single/Dual-Rate DAC with a Successive Bandpass Delta-Sigma Modulator Achieving <-67dBc IM3 within DC to 6GHz Tunable Passbands,” (Invited) IEEE J. Solid-State Circuits, Dec. 2018.
[2] Shiyu Su and Mike Chen, “A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <−80 dBc IM3 up to 1 GHz in 65 nm CMOS,” (Invited) IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 2963–2978, Dec. 2016.
[2] Shiyu Su and Mike Chen, “A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <−80 dBc IM3 up to 1 GHz in 65 nm CMOS,” (Invited) IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 2963–2978, Dec. 2016.
[1] Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma and Mike Chen, “A 12 bit 1GS/s dual-rate hybrid DAC with an 8GS/s unrolled pipeline delta-sigma modulator achieving > 75 dB SFDR over the Nyquist band,” (Invited) IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 896–907, Apr. 2015.
[1] Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma and Mike Chen, “A 12 bit 1GS/s dual-rate hybrid DAC with an 8GS/s unrolled pipeline delta-sigma modulator achieving > 75 dB SFDR over the Nyquist band,” (Invited) IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 896–907, Apr. 2015.
Shiyu Su, “Digital to radio frequency conversion techniques,” Ph.D. dissertation, 2019.
Shiyu Su, “Digital to radio frequency conversion techniques,” Ph.D. dissertation, 2019.
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