Embedded Files
Designer:
Designer:
Ce yang
Ce yang
Tapeout:
Tapeout:
TSMC 28nm, June 2023.
TSMC 28nm, June 2023.
Description (ISSCC 2025):
Description (ISSCC 2025):
A blocker-tolerant mmWave receiver with embedded ADC and DSP.
A blocker-tolerant mmWave receiver with embedded ADC and DSP.
Designer:
Designer:
Soumya Mahapatra
Soumya Mahapatra
Tapeout:
Tapeout:
TSMC 65nm, May 2023.
TSMC 65nm, May 2023.
Description (ISSCC 2025):
Description (ISSCC 2025):
A direct digital wireless transmitter with sub-harmonic switching power amplifier and hybrid DAC.
A direct digital wireless transmitter with sub-harmonic switching power amplifier and hybrid DAC.
Designer:
Designer:
Qiaochu Zhang*, Shiyu Su*, Zhengyi Qiu, Hsiang-Chun Cheng (*Equal Contribution)
Qiaochu Zhang*, Shiyu Su*, Zhengyi Qiu, Hsiang-Chun Cheng (*Equal Contribution)
Tapeout:
Tapeout:
TSMC 65nm, May 2023.
TSMC 65nm, May 2023.
Description (VLSI 2024):
Description (VLSI 2024):
An analog Boolean Satisfiability Problem (SAT) accelerator.
An analog Boolean Satisfiability Problem (SAT) accelerator.
Designer:
Designer:
Qiaochu Zhang*, Shiyu Su*, Baishakhi Rani Biswas (*Equal Contribution)
Qiaochu Zhang*, Shiyu Su*, Baishakhi Rani Biswas (*Equal Contribution)
Tapeout:
Tapeout:
GF 12nm, June 2022.
GF 12nm, June 2022.
Description (VLSI 2024, JSSC 2025):
Description (VLSI 2024, JSSC 2025):
Stochastic TDC with removal-free common-mode dithering and approximation adders.
Stochastic TDC with removal-free common-mode dithering and approximation adders.
Designer:
Designer:
Shiyu Su*, Qiaochu Zhang* (*Equal Contribution)
Shiyu Su*, Qiaochu Zhang* (*Equal Contribution)
Tapeout:
Tapeout:
TSMC 65nm, May 2022.
TSMC 65nm, May 2022.
Description (CICC 2023):
Description (CICC 2023):
A mostly-digital 2GS/s 8.5-bit ADC with segmented stochastic TDC.
A mostly-digital 2GS/s 8.5-bit ADC with segmented stochastic TDC.
Designer:
Designer:
Mayank Palaria, Shiyu Su, etc.
Mayank Palaria, Shiyu Su, etc.
Tapeout:
Tapeout:
TSMC 65nm, June 2022.
TSMC 65nm, June 2022.
Description (ESSIRC 2023):
Description (ESSIRC 2023):
First Kalman Filter IC with embedded ADC for sensor fusion.
First Kalman Filter IC with embedded ADC for sensor fusion.
Designer:
Designer:
 Hsiang-Chun Cheng, Shiyu Su, etc.
 Hsiang-Chun Cheng, Shiyu Su, etc.
Tapeout:
Tapeout:
TSMC 65nm, June 2022.
TSMC 65nm, June 2022.
Description (CICC 2023):
Description (CICC 2023):
First QP solver IC for micro-unmanned aerial vehicles.
First QP solver IC for micro-unmanned aerial vehicles.
Designer:
Designer:
 Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su
 Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su
Tapeout:
Tapeout:
TSMC 65nm, April 2022.
TSMC 65nm, April 2022.
Description (ISSCC 2023):
Description (ISSCC 2023):
A digital MDLL with adaptively linearized digital-to-time converter.
A digital MDLL with adaptively linearized digital-to-time converter.
Designer:
Designer:
 Ce Yang, Shiyu Su
 Ce Yang, Shiyu Su
Tapeout:
Tapeout:
TSMC 28nm, May 2021.
TSMC 28nm, May 2021.
Description (RFIC 2022):
Description (RFIC 2022):
A millimeter wave receiver front-end with embedded programmable mixed-signal filtering.
A millimeter wave receiver front-end with embedded programmable mixed-signal filtering.
Designer:
Designer:
Shiyu Su, Juzheng Liu, ALIGN(UMN)
Shiyu Su, Juzheng Liu, ALIGN(UMN)
Tapeout:
Tapeout:
FinFET 12nm, September 2020.
FinFET 12nm, September 2020.
Description (ICCAD 2021):
Description (ICCAD 2021):
A VCO array with automated layout generation.
A VCO array with automated layout generation.
Designers:
Designers:
Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho
Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho
Tapeout:
Tapeout:
TSMC 65nm, April 2020.
TSMC 65nm, April 2020.
Description (ISSCC 2021):
Description (ISSCC 2021):
AÂ ring-based digital PLL using a low-cost but coarse (<5 bits) time-to-digital converter to calibrate a high-precision (>11 bits) digital-to-time converter.Â
AÂ ring-based digital PLL using a low-cost but coarse (<5 bits) time-to-digital converter to calibrate a high-precision (>11 bits) digital-to-time converter.Â
Designer:
Designer:
Shiyu Su
Shiyu Su
Tapeout:
Tapeout:
TSMC 65nm, May 2019.
TSMC 65nm, May 2019.
Description (ISSCC 2020):
Description (ISSCC 2020):
A SAW-less direct RF transmitter with tri-Level time-approximation filter and reconfigurable dual-band delta-sigma modulation.
A SAW-less direct RF transmitter with tri-Level time-approximation filter and reconfigurable dual-band delta-sigma modulation.
Designer:
Designer:
Shiyu Su
Shiyu Su
Tapeout:
Tapeout:
TSMC 65nm, June 2018.
TSMC 65nm, June 2018.
Description (VLSI 2019):
Description (VLSI 2019):
A 1-5GHz direct RF transmitter with time-approximation filter achieving -158dBc/Hz out-of-band noise spectral density and -43dB EVM at 1024 QAM.
A 1-5GHz direct RF transmitter with time-approximation filter achieving -158dBc/Hz out-of-band noise spectral density and -43dB EVM at 1024 QAM.
Designer:
Designer:
Shiyu Su
Shiyu Su
Tapeout:
Tapeout:
TSMC 65nm, May 2017.
TSMC 65nm, May 2017.
Description (ISSCC 2018):
Description (ISSCC 2018):
A 16b 12GS/s single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands.
A 16b 12GS/s single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands.
Designers:
Designers:
Shiyu Su, Tzu-Fan Wu
Shiyu Su, Tzu-Fan Wu
Tapeout:
Tapeout:
TSMC 28nm, April 2016.
TSMC 28nm, April 2016.
Description:
Description:
A multimode hybrid DAC and a NUS ADC with dithering DACs for wireless transceivers.
A multimode hybrid DAC and a NUS ADC with dithering DACs for wireless transceivers.
Designer:
Designer:
Shiyu Su
Shiyu Su
Tapeout:
Tapeout:
TSMC 65nm, December 2016.
TSMC 65nm, December 2016.
Description:
Description:
A hybrid DAC with lowpass/bandpass/highpass delta-sigma modulator and image replica cancellation.
A hybrid DAC with lowpass/bandpass/highpass delta-sigma modulator and image replica cancellation.
Designer:
Designer:
Shiyu Su
Shiyu Su
Tapeout:
Tapeout:
TSMC 65nm, May 2015.
TSMC 65nm, May 2015.
Description (ISSCC 2016):
Description (ISSCC 2016):
A 12b 2GS/s dual-rate hybrid DAC with pulsed timing error pre-distortion and in-band noise cancellation achieving >74dBc SFDR up to 1GHz.
A 12b 2GS/s dual-rate hybrid DAC with pulsed timing error pre-distortion and in-band noise cancellation achieving >74dBc SFDR up to 1GHz.
Designers:
Designers:
Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma.
Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma.
Tapeout:
Tapeout:
TSMC 65nm, June 2013 .
TSMC 65nm, June 2013 .
Description (VLSI 2014):
Description (VLSI 2014):
A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz .
A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz .
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