Network on Chip
Introduction
A rapid progress in Very Large Scale Integration (VLSI) in the past recent years has resulted in the fabrication of millions of transistors on a single silicon chip. This advancement in the
micro-electronics leads to the integration of various components of a computing system or any other electronic system on a single Integrated Circuit (IC) to implement a complete system on a chip. Thus a paradigm called System on Chip (SoC) came into existence that refers to the system made up of interconnected cores or Intellectual Property (IP) blocks
on a single chip. So an effective communication system is required between the IP blocks of SoC [1]. Nowadays direct interconnections and mostly shared busses are used for onchip
communication. The problem with direct interconnections is that they are not scalable and become inefficient with an increase in the number of cores [2]. Shared buses do not give
satisfactory results when scaled beyond 8 to 10 cores.
Contention for the bus and arbitration also slows down the data movement. They are only good for the systems with less number of connections. So Network on Chip (NoC) is being
considered as the most suitable candidate for implementing interconnections in core based system on chip (SoC) design. In NoC paradigm, cores are connected to each other through a
network of routers and they communicate among themselves through packet-switched communication [2]
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REFERENCES
[1] W. Dally and B. Towles, “Route packets, not wires: onchip interconnection networks,” Proc. Design Automation Conference, Jun.2001, pp. 684–689.
[2] S.Kumar , A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg. et al, “A network on chip architecture and design methodology,” Proc. IEEE Computer SoCiety Annual Symposium on VLSI