Dynamic logic is used in the implementation of logic circuit for high speed designs such as data path in microprocessor [1]. However, it is not widely used because of its disadvantages like less noise robust and more power consuming compared to static logic style [2]. Domino logic is made by adding one inverter at the output of the dynamic gate. Domino gate has got advantage over the dynamic gate because fan-out of former is driven by inverter which has low output impedance and thus increases the noise immunity of the gate along with decreasing the output capacitance [3]. Figure 1 shows the standard domino logic style. Keeper transistor is used to maintain the logic one in the evaluation phase (CLK goes high) when there is charge leakage from the dynamic node through the pull down network (PDN). When PDN is ON in the evaluation phase dynamic node is discharged to zero through the PDN and evaluation transistor. Output inverter starts switching from zero to one and the keeper transistor starts turning OFF from ON. During this period there is static power dissipation from Vdd to Gnd.

During the evaluation phase small noise-signal at the input(s) of dynamic gate can change the desired output because of discharge of dynamic node. In worst case the circuit becomes

very less noise-tolerant in case of high-fan in OR gate implementations.

Noise robustness can be improved by upsizing the keeper transistor (making wider) which makes keeper (PMOS) more conducting and thus maintains the charge at the dynamic node

[4]. But this comes at the cost of static power dissipation which flows from Vdd to Gnd through keeper transistor when noise signal arrives at one of the inputs. To make dynamic circuit

more noise robust different circuit styles have been proposed [4-9].

Refer Link : http://dspace.nitrkl.ac.in/dspace/bitstream/2080/1517/1/Preetisudha_ICACCN.pdf

REFERENCES

[1] F. Frustaci M. Lanuzza P. Zicari S.Perri and P. Corsonello, “Low-power split-path data-driven dynamic logic,”IET Circuits Devices Syst.,Vol. 3, Iss. 6, pp. 303–312, 2009.

[2] Rakesh Gnana David J and Navakanta Bhat, “A Low Power, Process Invariant Keeper for High Speed Dynamic Logic Circuits,” IEEE International Symposium on Circuits and Systems, ISCAS, pp.1668, May 2008.

[3] J. Rabaey et al., Digital IntegratedCircuits, 2nd Edition, Prentice Hall.

[4] H.Mahmoodi-meimand and K. Roy, “Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style,” IEEE Trans. Very Large Scale Integr. Syst.

, 51, (3), pp.495–503, 2004.

[5] F. Frustaci P. Corsonello S. Perri and G. Cocorullo,“High-performance noise-tolerant circuit techniques for CMOS dynamic logic,” IET Circuit Devices Syst., vol. 2, No. 6, pp. 537-548, 2008.

[6] F. Mendoza-Hernandez, M. Linares-Aranda and V. Champac, “Noise tolerant improvement in dynamic CMOS logic circuit,” IEEE Proc.-Circuits Devices Systems, Vol 153, No. 6, pp.. 565-573, Dec 2006.

[7] O.Gonzalez-Diaz, M. Linares-Aranda and F. Mendoza-Hernaindez, “A Comparison Between Noise-Immunity Design Techniques for Dynamic Logic Gates,” 49th IEEE International Midwest Symposium on Circuits and Systems,MWSCAS '06, pp. 484 – 488, 2006.

[8] Fang Tang, Ke Zhu, Quan Gan and Jian Guo Tang, “Low-noise and power dynamic logic circuit design based on semi-dynamic logic,” 2nd International Conference on Anti-counte

rfeiting, Security and Identification, ASID 2008. 20-23 Aug. 2008.

[9] Atila Alvaizdpoul, Per Lurssoia-Edefors and Christer Sveizsson, “A Leakage-Tolerant Multi-Phase Keeper For Wide Domino Circuits,”Proceedings of ICECS '99. The 6th IEEE International Conference on Electronics, Circuits and Systems, pp.209, 1999.