Lab Resources

The VLSI laboratory at ECE Department of NIT Rourkela is obliged towards the support and encouragement of Ministry of Electronics and Information Technology, Government of India. The overall activities is purely supported by the Chips to Startup (C2S) Programme . 

Tutorials corresponding to various laboratories and EDA tools used in the laboratory are highlighted below. 

ASIC Lab 

(EC6272)

Faculty Advisor: Prof. Kamalakanta Mahapatra, NIT Rourkela, India

Prof. Ayas Kanta Swain, NIT Rourkela, India

Overview of the Laboratory setup and Computing Environment

List of EDA Tools - Cadence, Synopsis, AMD (Xilinx), Siemens (Mentor Graphics)

 Basic Knowledge

The development and manufacture of an ASIC design including the ASIC layout is a very expensive process. In order to reduce the costs, there are different levels of customization that can be used 

 Laboratory Manuals (Followed by UG/PG students and research scholars)

Laboraory manuals and Discussion - The laboratory activities reflects the work being conducted as an academic course work for post graduate students at NIT Rourkela India towards completion of graded work as assignment in a semester. The following hierarchy may be pursued (not mandatory) to understand part of the steps involved in the RTL to GDSII Integrated Circuit (digital) design semi-custom flow.




          Synthesis-II.pdf (Cadence Genus with Constraint)



      ATPG-II.pdf (Cadence Modus DFT Software SolutionSynopsys TestMAX™ ATPG for Scan Chain insertion - Sequential Design)






Further work on Signoff (two types of sign-off's: front-end sign-off and back-end sign-off) is on progress and will be updated soon. This tutorial is a work in progress, and needs updation frequently to be in compliance with the ongoing demands.


ASIC Lab (Followed prior to Year 2022)

(EC6272)

Faculty Advisor: Prof. Kamalakanta Mahapatra (Refer: Github Portal)

Overview of the Laboratory setup and Computing Environment

The VLSI laboratory at ECE Department of NIT Rourkela is obliged towards the support and encouragement of Ministry of Electronics and Information Technology, Government of India. The overall activities is purely supported by the Special Manpower Development Program for Chips to System Design (SMDP-C2SD) project

List of EDA Tools - Cadence, Synopsis, Xilinx, Mentor Graphics

 Basic Knowledge

The development and manufacture of an ASIC design including the ASIC layout is a very expensive process. In order to reduce the costs, there are different levels of customization that can be used 

·         Gate Array – This type of ASIC is the least customisable.  

·         Standard Cell – The mask is custom design, but the silicon is made from library components.

·         Full custom design – This involves the design of ASIC down to transistor level.

Introduction

As the demand for reduction of size is growing, System on Chip (SoC) has become the latest trend in today’s world. A SOC consists of an IC that has all the required digital and analog parts found in a system. For example a radio SOC has the PLL, power management, modulator, DAC, processing power on a single IC. Instead of a large circuit, we develop an entire system on a single chip. 

Development of an ASIC chip design needs the overall idea of specifications to manufacture design flow. To do so we first capture the specifications of the system. Then the system is divided into supports and functionalities of the system are listed out. Then the functions are converted in to a form of FSDM. This structure is then converted into a Hardware Description Language (HDL) code such as Verilog or VHDL. For the given code we also develop the test vectors to test it completely. 

A stage is reached henceforth, where we use a synthesis tool which converts the HDL code to a logic circuit. Such tools are developed by various Electronic Design Automation (EDA) organisations. This logic circuit is simulated with the test vectors and then corrected to perfection. Then all functions are clubbed to one system and are verified exhaustively for all its functions.

Then it is implemented on EDA tools and the layout is developed and tested for all deformities that can happen during manufacturing. This is then sent for fabrication and marketed. To develop the layout we use diagrams of predefined circuits (gates, muxes, decoders etc.), provided by fabrication units.

Old manuals (Followed prior to Year 2022)

 1. Manual for Experiment I 

2. Manual for Experiment II

3. Manual for Experiment III

4. Manual for Experiment IV (Part I),  Manual for Experiment IV (Part II)

5. Manual for Experiment V 

6. Manual for Experiment VI 

7. Manual for Experiment VII (Part I), Manual for Experiment VII (Part II)

8. Manual for Experiment VIII 

9. Manual for Experiment IX

Embedded Sytem Design Lab

(EC664, EC678)

Faculty Advisor: Prof. Kamalakanta Mahapatra

Instructor: Prof. Ayaskanta Swain

INTRODUCTION 

In the present scenario, topics like: Application Specific Integrated Circuit (ASIC), System- on Chip (SOC) have replaced Computer Architecture, Organization and design in the field of Computer Engineering. This shift has called for want of knowledge on Embedded System to be a pre-requisite. Majority of universities in India offers courses on micro controllers like PIC, ATMEL, MOTOROLA, INTEL etc. Few universities in India have taught ARM micro controller in their curriculum. There are several papers dealing with development of laboratory experiments using different platforms and different micro controllers [1, 2]. 

List of Equipment/Software : TI Boards, ARM Boards, TI, Altera, Microvision Keil

Paper dealing with development of laboratory exercises using Arm based micro controller are very less. On the other hand there is a vast development of technology with high performance micro controller like ARM and on software side the operating system Windows 8 can run on ARM micro controller has been developed.ARM micro controller is dominant in the mobile and auto mobile electronics market and is one of the industry leading standard micro controller. This is compatible with all four major platform operating systems Symbian os, Palm os, Linux os and windows CE. Keeping the above facts in view point, we thought that it is worthwhile to describe a platform on which a series of experiments can be performed that gives a hands –on experience and bringing in a take home concept. Further, the series of experiments described in this laboratory can be introduced as a part of curriculum for the senior graduate students. 

A. ARM7TDMI

 ARM (Advanced RISC Machine) architecture is the 32 bit RISC instruction set architecture which is most widely used in a number of embedded systems. ARM is a leading intellectual property provider of high performance, low cast, and power efficient RISC processor micro controller [3]. ARM processor has some characteristics that made them suitable for low power application such as intelligent voltage management and cache micro architecture. The most prominent future that makes ARM differ from other micro controllers is [4]

ARM CPU has a von Newman architecture and it uses two buses i.e. AHB (advanced high performance bus) and VPB (VLSI peripheral bus) which increases the speed of execution [5] compared to other commonly used microcontroller such as the INTEL 8051 and the Microchip PIC family. ARM family provide wide range of performance from 100 MIPS to 1000 MIPS. This increase in performance leads to two important factors and advances in a new process technology.  New pipeline mechanism.  Implementation of Harvard bus architecture in ARM9 family An efficient and optimized processor design is an art. This is because the instruction set should cater the need of the programmer in an efficient way. i.e. keeping the future implementation also plays pivotal role in the processor design .This is because it has to bridge the gap between HLL construct and machine language. Thus the compiler design which in turn depends on the type of instruction set. The whole ARM family has the same instruction set of 32 bit ARM instruction set and 16 bit thumb instruction set .The thumb instruction set was introduced in the fourth version of the ARM architecture in order to achieve the high code density for embedded applications. 

Resources

There is open source KEIL software that provides a best development tool and technical support [6]. It also offers numerous ways from the technical support that one needs to complete embedded projects. KEIL supports simulation using the target systems and a debugger interface. Micro vision includes traditional features like simple and complex breakpoints, watch windows and execution controls as well as sophisticated features like trace capture, execution profiler, code coverage and logic analyser. 

REFERENCES

 [1] Yao Li “Teaching Embedded Systems using a modular Approach Microcontrller Training Kit”, World Transactions on Engineering and Technology Education. Vol.6, No.1, PP-135-138, 2007. 

[2] Feisel. L and Rosa A “The role of the Laboratory in undergraduate Engineering Education’ Journal of Engineering Education . 94,121,005.

 [3] Oliver J.P and Haim. F “Lab at Home Hardware Kits for a Digital Design Lab” IEEE Tranactions on Education 52, PP46, 2009. 

[4] Andrew N Sloss “ARM Systems Developers Guide: Design and Optimising System software, Morgan Kaffman Publishers, An Import of Elsevier, 2005.

 [5] Stew Furbur “ ARM System –on-chip Architecture, Pearson Education, 2005 

[6] http://www.keil.com