Prof. Gaurav Verma - Research interests

LinkedIn Profile https://www.linkedin.com/in/gaurav-verma-659850b1/

Looking forward into Reinforcement learning and Generative AI learning

Hardware for next generation AI hardware

Deep Learning: Computer Vision Applications- Image Denoising and Image Recognition, Developing Training and Inference Architecture for Neural Networks

Spintronics: STT-MRAM, SOT-MRAM, Domain wall devices, Skyrmions based devices, Spin based Oscillators, Fanout in spin systems, Modelling of spin based device and circuits, Multiferroic devices

Digital and Analog Circuit Design: Digital VLSI Design, Circuits and Layout Designs

VLSI Architecture Design: Architectures for implementation of Convolutional Neural Network using MRAM integrated CMOS

Implementation on Hardware: FPGA (Basys3 supported board).

Neuromorphic computing and architectures using non-volatile memory devices

Artificial Intelligence, Computer architecture

Image processing, Graphics Visualization and Volume Graphics, Image Processing Fractional Transform Theory, Wavelet Analysis, Medical Imaging, Long-Range Imaging, Hyperspectral Imaging, Machine Learning, Pattern Recognition, Multilingual Text Recognition, EEG based Pattern Analysis.

Algorithm and Architectures for Intelligent Machine Vision

Nanoscience, materials science, spintronic applications, and magnetic phenomena

Light Fidelity

e-agriculture, IoE, agri-smart electronics

- Key Expertise –

Digital and Mixed Signal Design ~Electronics and VLSI ~Teaching ~Project Management & Execution ~ Strategic Planning ~ Team Management

Software Proficiency Coding: Python (Neural Network Architecture Design), MATLAB (Mathematical Modeling), VHDL (Behavior, DataFlow and Structural Design of Digital Design), Verilog-A (Analytical Modeling of Devices)

Tools: Cadence Virtuoso (Circuit Design and its Transient, DC, and AC analysis on ADEL Environment, MonteCarlo Analysis, and Layout Design), Synopsis HSPICE (Circuit Design), Mumax3 (Physics based Device Modeling and Simulation of Spintronic Device), Vivado, Synopsys- DC & IC Compiler, MNSim, NeuroSim, Destiny, NVSim, Gem5, COMSOL

Technologies: Deep Learning (Pytorch, Tensorflow)

Documentation: Latex, Word

Scripting

Machine Learning

Matlab and Python projects

Robotics and IoT : AVR, ARM, Atmega, 8051, Arduino, Robosapiens Quadcopter, Accelerometer

During my engineering degree in Electronics pursued from Bhaskaracharya College of Applied Sciences, University of Delhi, I focused on Analog and Digital Electronics subjects with Signals and Systems, Microcontrollers, Embedded Systems. My interaction with robotics and communication field nurtured with the workshops attended during the course. I presented the topic ‘Light Fidelity’ during a symposium celebrating ‘International Year of Light’. Then I moved forward in the same field with my final year project titled ‘Light-Fidelity – A Helping Hand in Digital India Initiative’ and published my first paper based on my project work. I also got an opportunity to lead a team of 10 members for an innovative project of university based on Microbial Fuel Cells (MFC). A poster, an abstract and a conference paper were published during course of the project. I was fascinated by the NPTEL course contents and completed two certification courses in “VLSI Technology” and “Introduction to Programming in C” during second year of my undergraduate study.

In the final year of engineering I got placed in few MNCs (Amazon, Triyaam Vision) however I opted for higher education over job for self-satisfaction and for pursuing my passion I qualified Gate 2017 with a score of 359 and enrolled for Masters of Technology in VLSI Design at CDAC Mohali. It provided me an immense learning environment in the field of IC design and core electronic concepts. The practical experience achieved during the course work aroused my zeal towards VHDL, Verilog and FPGA. Image processing became my focus of interest during a workshop at IIT Roorkee which revealed the domains and future scope of the same. I was selected under a DST-SERB project and opted for thesis with the continuation of the same titled ‘FPGA Implementation for Detection of Rice Hispa and Stem Borer on Rice Crop’. The concepts of K-means clustering, SVM classification and ANN were the focus areas during the project. I interacted with my batch-mates to get in-depth knowledge about techniques of FinFET and CNTFET and low power design domain.

Apart from Cadence Design Systems, I have been interviewed by companies including Vicharak, Global Foundaries, Synopsys, STM, NXP, Turing in the VLSI semiconductor industry. I am working towards enriching my profile and skills related to Verilog, SV, and UVM for R&D oportunity in corporate.

In academics, my vision is to be HoD and Dean Director of my department with goal to be a part of reputed government college such as Lucknow university and IET (AKTU) to parse my skills for upliftment of education sector in my home town.

My first job was as a Research Developer in 2017.

I have completed doctoral degree from Electronics and Communication Engineering department, IIT Roorkee under the supervision of Late Dr. Brajesh Kumar Kaushik. I have joined my PhD in July, 2019 and my area of research include spintronics based image processing, spiking and non-spiking neural networks. In my B.Tech and M.Tech education, I’ve completed a great deal of coursework on controller based applications and coding, circuit design tools and modelling tools including SPICE, Cadence, Matlab to mention a few. I learned and applied skills such as FPGA programming, Verilog coding, python and machine learning with relevant projects. In addition, I spent the past one year at IIT Roorkee in developing skills related to Vivado tool, image processing, computer vision, smart monitoring cameras, hardware implementation of neural networks and machine learning concepts. Volunteering with the PhD research group under guidance of my supervisor has also helped me grow my skills in team collaboration, verbal communication and project leadership.

I believe and try to work towards betterment of society and environment as a whole. I keep looking for novel inventions and contributions made by researchers making life better. A recent example is of chain-less bicycle (https://nubikemfg.com/).

An approach for Enhancing The Performance of Microbial Fuel Cell :

A Green Energy Initiative

Ajay Aggarwal1 GauravVerma2 Yogesh Singh3 Anjali Kumari4 Sanjeev Kumar5 Om Ji Agnihotri6 Sushmita7 Avantika Shrivastav8 Shaoni Bhattacharya9 Mansi Singh10

Mr. Pawan Kumar11 Dr.Inderbir Kaur12 Dr.RuchiGulati Marwah13 Dr. GeetaMongia14

Prof. Avinashi Kapoor15

1-10 Student Research Group, Bhaskaracharya College of Applied Sciences, University of Delhi, 11Assistant Professor, Department of Instrumentation, Bhaskaracharya College of Applied Sciences, University of Delhi, 12,14Associate Professor, Department of Electronics, Bhaskaracharya College of Applied Sciences, University of Delhi,13Assistant Professor, Department of Microbiology, Bhaskaracharya College of Applied Sciences, University of Delhi

15Professor, Department of Electronic Science, South Campus, University of Delhi

The world is on the verge of “Global Energy Crisis” as the Non-Renewable sources of energy like petrol, oil, etc. are limited, expensive and environment polluting. To address the concern, a major effort has been made towards clean and green electricity generation through Microbial Fuel Cell (MFC) technology. MFC is a bio-electrochemical device designed for electricity generation in the process of wastewater treatment. It consists of four parts, (1) Anode chamber filled with organic matter (anaerobic condition), (2) Cathode chamber filled with water (aerobic condition), (3) Proton selective membrane separating two chambers and (4) external circuit connecting anode and cathode. Decomposition of organic matter by bacteria produces electrons that flow through external circuit and protons that pass through membrane thereby producing electricity. In the present work, A MFC was constructed and the effect of seeding on the power generating ability of bacteria present inherently in the sewage samples was studied. It was found that the performance was enhanced with the seeded sewage sample and adequate amount of open circuit voltage was measured. This, ensures that seeding is one of cheaper and promising solution for uplifting the scope of MFC in commercial applications. Hence, seeded- MFC is found to be the one of the promising technology of future for cost effective clean electricity generation. MFC has various applications such as energy source for small electronic devices, bio-sensor for BOD measurement, wastewater treatment, hydrogen production, etc.

Revealing the potential of spin-based spiking neural networks

Abstract— The systems utilizing machine learning techniques require extensive computations including vector-matrix multiplication. The traditional von Neumann architecture is inefficient in the hardware implementation of such systems. It is therefore required to draw motivation from unconventional but more computationally influential architectures inspired by biological brain. The human brain is an inspiration for a power-competent learning system that solves complex computational tasks in a resource-efficient manner. There is a need for future hardware solutions with biologically inspired network functionality. Non-volatile memory devices with the capability of performing computation in memory are used for hardware implementation of complex networks. This article presents spin-based memory devices and their implementation for bio plausible spiking neural networks (SNNs). Spin based devices provide non-volatility, high endurance, scalability, CMOS compatibility and ultra-low power consumption. The spiking functionality in neurons can be easily mapped for various spin devices with synaptic learning, hence paving the path for future hardware solutions.

Index Terms— Bio plausible, machine learning, neural architecture, spiking neural network, synaptic learning.

Emerging Memory Devices for Unconventional Computing

The scaling down of CMOS feature size down to the atomic length has resulted in high device leakage and performance instability. Moreover, the data-intensive tasks in conventional von-Neumann computing systems result in significant latency, bandwidth, and energy consumption due to memory wall problems. The unconventional computing architectures such as in-memory computing, neuromorphic computing, stochastic/probabilistic/approximate computing and quantum computing are the promising solutions to address these issues. The development of emerging memory devices such as spintronic devices, resistive random-access memory (ReRAM), phase-change memory (PCM), ferroelectric field-effect transistor (Fe FET) etc. have satisfied the ever-increasing requirements of low energy, high scalability, good CMOS compatibility, high reliability, and high performance for these unconventional computing systems. Increasing demands for the application of unconventional computing paradigm has led to the growth of the global emerging memory market. According to Verified Market Research, the market size of emerging non-volatile memory technologies is projected to reach $138.48 Billion by 2028, growing at a compound annual growth rate (CAGR) of 8.9% from 2021 to 2028. Despite huge advancements, crucial challenges still remain before such emerging devices and computational systems to replace the traditional von-Neumann computing architecture.

The goal of this summer school is to provide participants with academic exposure to recent developments, challenges, and future trends in the field of unconventional computing by exploiting emerging devices. Its main objective is to foster communication among physicists, engineers from academia and industry, and researchers working on nanodevice-based computing systems. During the event, participants and experts will exchange ideas, which will serve to inspire new applications in this interesting field. Through this summer school, participants will have the opportunity to collaborate on research, network with colleagues, and participate in future conferences conducted by IEEE NTC. IEEE NTC Student Chapter, IIT Roorkee will help coordinate and publicize activities that are occurring in the region. The membership drive will be conducted during the summer school to enhance the sense of inclusivity and engagement among professionals, researchers, and enthusiasts in the field of nanotechnology and nanoscience. This will further help in establishing stronger connections among researchers, facilitate interdisciplinary collaborations, and promote the exchange of ideas, ultimately advancing the field of nanotechnology and driving innovation forward.

RESEARCH PROJECTS:-

1. Image Processing using spin devices: Image pre-processing techniques play an important role for analysis of visual data. Convolution serves as the basic computational primitive for various associative computing tasks ranging from edge detection to image matching. The primary objective of the research work will be focused on design and implementation of efficient image processing architecture using spin devices. The objective includes edge detection, filtering, segmentation and image restoration targeted for binary, grayscale and RGB image formats. This will be extended to applications of object recognition such as pupil detection. The aim is to lower the power consumption (read/write/reset) of spin-based devices during operation performed for image processing SOT/DW device based feature extraction for edge detection using crossbar array. The objective is to design the IP core of a video image edge detection system on the EDK. The hardware circuit of the algorithm is to be achieved on Xilinx/Vivado and simulations using the Model Sim tool. To evaluate energy consumption in edge detection algorithms using spin based devices and comparison with conventional methods. Implementation of edge detection algorithms using hybrid spin networks to utilize swarm intelligence using the concept of memristive networks. Study of impact of various parameters of the spin devices on the efficacy of the implementation.

2. Efficient spin based neuromorphic computing systems (NCSs) design: Image classification tasks using spin devices achieve the state of art accuracy at very low energy consumption. A compact, energy-efficient magnetic neuron, which can directly be cascaded to a spin-based crossbar array of synapses to eliminate additional interfacing circuitry. Spintronic neurons that allows them to compute multiple critical convolutional neural network functionalities simultaneously and in parallel, saving space and time Development of a device-to-system-level behavioral model to underscore the applicability of the system in all image recognition applications The third objective of the research will be focused on achieving the desired accuracy with minimized loss in F score. Such improved performance can be extended to more complex motion detection. The algorithmic level performance measure with respect to device level variations is to be achieved. Design and simulation of CNN accelerator using spin devices. To implement a high - density cross-point spintronic synapse array with improved synaptic characteristics for EEG and other pattern recognition. The aim is to utilise LUT based simulation framework for achieving optimum performance in image processing and machine learning applications. Training spin based (SOT/DW) XNOR network for optimised and energy efficient image processing. Effective software implementation of complex neuromorphic networks, with device variability sufficiently low to allow operation of integrated neural networks. To design a hybrid memristive device framework for machine learning tasks. Codesign for stochastic computing utilizing the stochastic switching characteristics of devices (along with algorithms) based on nanoscale non-volatile technologies.

3. Performance optimization for spin-based hardware accelerators: Hardware implementation of efficient neural network architecture for image classification Convolution serves as the basic computational operation for various image processing tasks. CMOS implementation of such computations face bottlenecks in area and energy consumption due to the large number of multiplication and addition operations involved. An ultra-low power and compact hybrid spintronic-CMOS design for the convolution. computing unit is the second objective of this research work. The hardware mapping of a feed-forward DNN comprising of multiple hidden layers of neurons connected in an all- to-all fashion to an output layer Spintronic synapses are present at each cross-point of the array and the conductance of the device encodes the value of the corresponding synaptic weight. The back propagation and feed forward algorithm have trade-off with the weight precision and accuracy The aim is to achieve backpropagation algorithms and weight update scheme on hardware for generalized cross bar array structure using spin devices. To design a low power and scalable spiking network accelerator for edge detection. utilizing potential divider arrangement of spin devices to indicate difference in frequencies between spike trains. The aim to design a complete framework for training and inference using all spin non-spiking neural networks. To make a significant contribution to the realization of future spin-based ANN applications using SOTDMI-based CIDWM-MTJ. Implementation in micromagnetic framework for a spin orbit torque driven domain wall based synaptic device for on chip learning of FCNN. To implement ex-situ training approaches for spin device crossbars that account for sneak paths and the stochasticity inherent in device switching.

4. Design and implementation of spiking neural networks: For recognition and classification tasks, biological systems are much better in terms of performance and energy efficiency Building blocks of all such biological systems are neurons and synapses. The various neuron models and synaptic learning algorithms can be mapped to spin devices by exploiting noisy device characteristics. The aim will be to design brain- inspired stochastic models using spin devices and to develop the learning algorithms for spiking neural networks. The other features targeted include spike count based homeostasis, adaptive synaptic plasticity (ASP) for efficient feature learning.

5. Framework design for spin device-based bio-plausible system: The last targeted work includes stochastic STDP algorithm and its circuit level implementation for Hebbian/ Anti Hebbian learning. A forced-learning methodology to achieve efficient synaptic plasticity in such stochastic SNNs. Synaptic plasticity is achieved by the stochastic switching of the MTJ conductance states, based on the temporal correlation between the spiking activities of the interconnecting neurons. Long term/short term synaptic plasticity to achieve learning efficiency for supervised/unsupervised as well as partially supervised learning approaches. This will be used for a complete paradigm design for spin based spiking CNN architecture and applications in edge computing devices.

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