Hello, I'm Prashanth H C.
VLSI Research student at IIITB, and
Senior Engineer at Mediatek for Sytem Level Cache-SLC (L3/LLC cache) verification.
ನಮಸ್ತೆ,
ನಾನು ಪ್ರಶಾಂತ್
Seeking challenging opportunities in VLSI industry in Architecture design/analysis.
Good research track record, hands-on experience in full RTL to GDS flow and AI accelerators.
Publications : Research work
Recommendation letters are available on request, please write to prashanthhcp@gmail.com
Resume :
Last updated - July 2023
Please visit the projects tab on top to view some interest work.
Prashanth H C.pdfWorked under Dr.Madhav Rao, and was affiliated to HiDES and Hardware for AI labs.
My thesis benchmarks various CNN architectures on traditional CPU and GPU, and characterizes various edge accelerators including DPUCZDX8G (Xilinx zynq SOC), Vision P6 (Cadence DNN IP), edgeTPU and few other accelerators using Resnet based CNNs. I use the recent SOTA solution on ImageNet for edge devices : Once-For-All NAS to search for hardware constrained CNN architectures with a wide range of compute and memory requirement. Searched architectures are characterized using cycle accurate simulators, analytical performance models or on-device measurement. Using roofline analysis the obtained results are used to benchmark the accelerator architecture with relevance to memory-to-compute capacity, impact on the latency, and energy. Evolutionary search is used to obtain the most efficient network architecture for accuracy, with a given hardware constraint.
I also perform roofline analysis of the most common CNN architectures used today on traditional workstation, edge(mobile) CPU and GPU.
Thesis is available on request.
Furthermore, few additional work :
Algorithmic- computer architecture optimization
Architecture optimization and profiling of systolic arrays for different workloads.
Design of accelerator components, Multi-objective accelerator-architecture co-design of Capsule Neural Networks.
Evolutionary circuit, system design
Standard Cell Library design with arithmetic cells developed using evolutionary algorithms.
CMOS circuit optimization using heuristic algorithms.
Design and analysis of log, anti-log circuits.
Approximate Computing
A Probabilistic Approach to Design Inexact Compressors for Approximate Booth Multipliers.
A merged hybrid MAC for CNNs.
Approximation - tunable Floating point multiplier.
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