Full Path
(Teachers)
What is included here?
Each subpage contains teacher slides, student slides, activities, and quizzes.Β
This path picks up after the Foundational Path and is more in depth than the partial path, with how to create a Verilog script which is then sent to OpenROAD for Synthesis and Place & Route (students learn what these process entail and what occur), then receive a complete .gds file that can be sent to verification to create a chip.Β
Students will work on the additional portions of the design cycle to complete a full chip design. This produces a complete .gds that can be fabricated by any foundry.
This is a Module about learning how to make a silicon chip and the process that goes into making it. This set of lessons are focused on the OpenROAD flow.Β We will be posting our lessons, presentations, labs and other resources.Β This is primarily a Resource Page, so that means it's a Mish-Mash of Silicon Wafer process content.Β Β
We are huge supporters of Open Source and Creative Commons resources.Β This is another way of saying Free, Equitable and Accessible resources...Β Β
OPEN SOURCE
Contribute Here
All of the content created has been created to be open sourced for all teachers. If you would like to contribute to this, please use this template to submit activities to this drive link to add to community resources.Β
https://www.ictworks.org/the-dial-open-source-community-maturity-model/
Lesson Topic - Logic Gates and Making a Silicon Chip:
Do You Need To Build A New Clean Linux Build?
If you need to build Linux...
Check out this short Ubuntu Linux Build Instructions for the Image I use in class.
Here is the Ubuntu Clean Build Shell Script I'm using
wget -O Ubuntu-Clean-Build.sh https://raw.githubusercontent.com/jimTheSTEAMClown/Linux/master/Ubuntu-22-04-2-CleanUpdate.sh
chmod 744 Ubuntu-Clean-Build.sh
./Ubuntu-Clean-Build.sh
OpenROAD - Let's Build A Chip:
OpenROAD Lessons
High School OpenRoad Program:
Working in conjunction with theopenroadproject.org, the goal of this OpenROAD Highschool teaching module is Β to bring a replicable set of lessons and labs that can be taught by any STEAM teacher over a 4-8 weeks time frame.Β The plan is to provide a set of lessons and Labs that will cover the OpenROAD design tools and flow, so students can learn and understand what it take to create a chip.Β The introductory lessons will cover the Silicon Chip industry and the career path to becoming a VLSI Chip designer.Β The lessons and labs will then walk the students through the Open ROAD design process.Β Students will create a chip design that is ready for submission,Β by implementing Initial tools and flow for Synthesis, Placement Setup, Floorplanning, Pin placement, Using Macros and other Structures, Checking and Adjusting Timing and Placement, Chip file submissions.
The New Official Google Site is here: OpenROAD Project
The Canvas source class build area is here Canvas - OpenROAD Project
OpenROAD Highschool Github site (STEAM Clown)
OpenROAD Highschool Github site (OpenROAD)Β
Open ROAD - Introduction
In this lesson you will get an overview of the OpenROAD project, the OpenROAD golas, and an introduction to the OpenROAD flows. What is the goal of OpenROAD
Lesson Resources:
OpenROAD Introduction - π° Slide Presentation (Update Coming)
OpenROAD Introduction - π Lesson Tutorial - (Planned Spring 2024)
OpenROAD Introduction - π½οΈ π§Video - (Planned Spring 2024)
OpenROAD Introduction - LAB #1 - π οΈ LAB Activity - (Planned Spring 2024)
OpenROAD Introduction - LAB #2 - π οΈ LAB Activity - (Planned Spring 2024)
OpenROAD Introduction - LAB #3 - π οΈ LAB Activity - (Planned Spring 2024)
Open ROAD - Tools and Project Installation & Build Steps
In this lesson you are going to learn the steps to create your first Open ROAD project.Β You will learn the options to execute the following steps:
Install or upgrade a Linux image on a computer or setup a virtual machine
Run the setup scripts (An automated shell setupOpenROAD.sh will be provided to do most of the heavy lifting)
Setup the Visual Studio Code tools
Validate your install is good and completed without errors
Lesson Resources:
OpenROAD - Tools and Project Installation - π° Slide Presentation - (Update Soon)
OpenROAD - Tools and Project Installation - π Lesson Tutorial - (Planned Spring 2024)
OpenROAD - Tools and Project Installation - π½οΈ π§Video - (Planned Spring 2024)
OpenROAD - Tools and Project Installation - LAB #1 - π οΈ LAB Activity - (Planned Spring 2024)
OpenROAD - Tools and Project Installation - LAB #2 - π οΈ LAB Activity - (Planned Spring 2024)
OpenROAD - Tools and Project Installation - LAB #3 - π οΈ LAB Activity - (Planned Spring 2024)
Open ROAD - Pre-Built - Project Introduction
In this lesson you are going to explore the running of the pre-installed example designs.Β You will validate the tools and projects are installed correctly and have the ability to run some verification scripts on a default build of the GCD (Greatest Common Divisor) design. You will learn the steps to create your first Open ROAD Design. Explore / Review the following project features:
Directory locations for pre-built source files
Directory, Module and File naming conventions
Config andΒ Constraint parameters and settings
Running the make flow
Validating your design process correctly
Lesson Resources:
OpenROAD - Pre-Built Project Introduction Exploration - π° Slide Presentation - (Draft for DAC - July 2023)
OpenROAD - Pre-Built Project Introduction Exploration - π Lesson Tutorial - (Planned Spring 2024)
OpenROAD - Pre-Built Project Introduction Exploration - π½οΈ π§Video - (Planned Spring 2024)
OpenROAD - Pre-Built Project Introduction Exploration - LAB #1 - π οΈ LAB Activity - (Planned Spring 2024)
OpenROAD - Pre-Built Project Introduction Exploration - LAB #2 - π οΈ LAB Activity - (Planned Spring 2024)
OpenROAD - Pre-Built Project Introduction Exploration - LAB #3 - π οΈ LAB Activity - (Planned Spring 2024)
Open ROAD - Your First Verilog Project - Building A Verilog Counter Design
In this lesson you are going to explore the creation of your first Verilog OpenROAD Project.Β You will learn the steps to create your first Open ROAD Design. Explore / Review the following project features:
Directory locations for Verilog source files
Directory, Module and File naming conventions
Config andΒ Constraint parameters and settings
Running the make flow
Validating your design process correctly
Lesson Resources:
OpenROAD - Building A New Verilog Counter Design - π° Slide Presentation - (Draft for DAC - July 2023)
OpenROAD - Building A New Verilog Counter Design - π Lesson Tutorial - (Planned Spring 2024)
OpenROAD - Building A New Verilog Counter Design - π½οΈ π§Video - (Planned Spring 2024)
OpenROAD - Building A New Verilog Counter Design - LAB #1 - π οΈ LAB Activity - (Planned Spring 2024)
OpenROAD - Building A New Verilog Counter Design - LAB #2 - π οΈ LAB Activity - (Planned Spring 2024)
OpenROAD - Building A New Verilog Counter Design - LAB #3 - π οΈ LAB Activity - (Planned Spring 2024)
Open ROAD - Virtual Studio Code - Project Introduction - Planned Spring 2024
Digital Logic - OpenROAD - Visual Studio Code Project Introduction Exploration - π° Slide Presentation (Coming Soon - Placeholder Link)
Digital Logic - OpenROAD - Visual Studio Code Project Introduction Exploration - π Lesson Tutorial
Digital Logic - OpenROAD - Visual Studio Code Project Introduction Exploration - π½οΈ π§Video
Digital Logic - OpenROAD - Visual Studio Code Project Introduction Exploration - LAB #1 - π οΈ LAB Activity
Digital Logic - OpenROAD - Visual Studio Code Project Introduction Exploration - LAB #2 - π οΈ LAB Activity
Digital Logic - OpenROAD - Visual Studio Code Project Introduction Exploration - LAB #3 - π οΈ LAB Activity
Open ROAD - Verilog Synthesis - Planned Spring 2024
OpenROAD - Verilog Synthesis Flow - π° Slide Presentation (Coming Soon - Placeholder Link)
OpenROAD - Verilog Synthesis Flow - π Lesson Tutorial
OpenROAD - Verilog Synthesis Flow - π½οΈ π§Video
OpenROAD - Verilog Synthesis Flow - LAB #1 - π οΈ LAB Activity
OpenROAD - Verilog Synthesis Flow - LAB #2 - π οΈ LAB Activity
OpenROAD - Verilog Synthesis Flow - LAB #3 - π οΈ LAB Activity
Open ROAD - Floor Planning - Planned Spring 2024
OpenROAD - Floor Planning Flow - π° Slide Presentation (Coming Soon - Placeholder Link)
OpenROAD - Floor Planning Flow - π Lesson Tutorial
OpenROAD - Floor Planning Flow - π½οΈ π§Video
OpenROAD - Floor Planning Flow - LAB #1 - π οΈ LAB Activity
OpenROAD - Floor Planning Flow - LAB #2 - π οΈ LAB Activity
OpenROAD - Floor Planning Flow - LAB #3 - π οΈ LAB Activity
Open ROAD - Placement - Planned Spring 2024
OpenROAD - Placement Flow - π° Slide Presentation (Coming Soon - Placeholder Link)
OpenROAD - Placement Flow - π Lesson Tutorial
OpenROAD - Placement Flow - π½οΈ π§Video
OpenROAD - Placement Flow - LAB #1 - π οΈ LAB Activity
OpenROAD - Placement Flow - LAB #2 - π οΈ LAB Activity
OpenROAD - Placement Flow - LAB #3 - π οΈ LAB Activity
Open ROAD - Clock Tree Synthesis (CTS) - Planned Spring 2024
OpenROAD - Clock Tree Synthesis (CTS) - π° Slide Presentation (Coming Soon - Placeholder Link)
OpenROAD - Clock Tree Synthesis (CTS) - π Lesson Tutorial
OpenROAD - Clock Tree Synthesis (CTS) - π½οΈ π§Video
OpenROAD - Clock Tree Synthesis (CTS) - LAB #1 - π οΈ LAB Activity
OpenROAD - Clock Tree Synthesis (CTS) - LAB #2 - π οΈ LAB Activity
OpenROAD - Clock Tree Synthesis (CTS) - LAB #3 - π οΈ LAB Activity
Open ROAD - Routing Flow - Planned Spring 2024
OpenROAD - Routing Flow - π° Slide Presentation (Coming Soon - Placeholder Link)
OpenROAD - Routing Flow (CTS) - π Lesson Tutorial
OpenROAD - Routing Flow (CTS) - π½οΈ π§Video
OpenROAD - Routing Flow - LAB #1 - π οΈ LAB Activity
OpenROAD - Routing Flow - LAB #2 - π οΈ LAB Activity
OpenROAD - Routing Flow - LAB #3 - π οΈ LAB Activity
Stuff to Sort / Develop / Or Delete
The-OpenROAD-Project Intro
OpenROAD RTL-GDSII simulation and verification flow
Building blocks of open-source design (this should introduce .libs. .v source and public pdks briefly if not covered in the previous module covering RTL-GDSII)
Running the OpenROAD flow from RTL-GDSII (key stages and intermediate results briefly)
Key advantages and features of OpenROAD flow
OpenROAD GUI Introduction
Validating the design for Tapeout - My First Chip Labs - 4-5 labs that incorporate the following steps, to complete a design ready for submission
Lab #1 - Initial tools and flow for placement setup
Initialize floorplan - define the chip size and cell rows
Place pins (for designs without pads )
Lab #2 - Using Macros and other Structures
Place macro cells (RAMs, embedded macros)
Insert substrate tap cells
Insert power distribution network
Macro Placement of macro cells
Global placement of standard cells
Lab #3 - Checking and Adjusting Timing and Placement
Repair max slew, max capacitance, and max fanout violations and long wires
Clock tree synthesis
Optimize setup/hold timing
Lab #4 - Finishing Touches
Insert fill cells
Global routing (route guides for detailed routing)
Antenna repair
Detailed routing
Parasitic extraction
Lab #5 - Final Analysis
Static timing analysis
Contributing to the open-source design community using the OpenROAD ecosystem
Each lecture and lab modules will contain the following collateral and curriculum so that a STEAM teacher anywhere in a Highschool or Community College can implement the course work.Β
Modules deliverables will include: (about 4 hours of 30 min Lectures & 8+ hours of Lab & Assessment activities)Β
Google Docs: π° Slide Presentation / πΌοΈ Lesson Tutorial / β¨ Resources
Canvas LMS Module: π οΈ LAB Activities and π Formative & Summative AssessmentsΒ